alter unit tests to match change in CSR table format

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index ddf951aab96c6ed422683ff7b1602868437e8cde..b3b06c03127fa0d0bf709b4797141890dd2bfdab 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -1,15 +1,14 @@
-#define SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
-  (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<14) | (packed<<15))
+#define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \
+  (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15))
+#define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \
+  (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15))
 
-#define SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
-  (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (active<<14))
-
-#define SET_SV_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
-        li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ); \
+#define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \
+        li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
         csrrw  x0, 0x4c0, x1
 
-#define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
-        li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, active ); \
+#define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \
+        li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \
         csrrw  x0, 0x4c8, x1
 
 #define SET_SV_2CSRS( c1, c2 ) \

diff --git a/isa/rv64uc/sv_c_lwsp.S b/isa/rv64uc/sv_c_lwsp.S
index d643594e8540271203a5499cf56f5507c6e71c36..e30d11abac647043d088657ce161e22b7b152be9 100644 (file)
--- a/isa/rv64uc/sv_c_lwsp.S
+++ b/isa/rv64uc/sv_c_lwsp.S
@@ -22,8 +22,8 @@ RVTEST_CODE_BEGIN
         li          a4, 0 
 
         SET_SV_MVL(3)
-        SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1, 0),
-                      SV_REG_CSR(1, 2, 0, 2, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1),
+                      SV_REG_CSR(1, 2, 0, 2, 1) )
         SET_SV_VL(3)
 
   mv a1, sp

diff --git a/isa/rv64uc/sv_c_lwsp_predication.S b/isa/rv64uc/sv_c_lwsp_predication.S
index d2caf8be6768d04661cd764e900e4dfab0b7a1ce..a0a293434e492d9ae34277a71cd6b3855418fec1 100644 (file)
--- a/isa/rv64uc/sv_c_lwsp_predication.S
+++ b/isa/rv64uc/sv_c_lwsp_predication.S
@@ -28,11 +28,11 @@ RVTEST_CODE_BEGIN
   la sp, data;
 
         SET_SV_MVL(3)
-        SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1, 0),
-                      SV_REG_CSR(1, 2, 0, 2, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1),
+                      SV_REG_CSR(1, 2, 0, 2, 1) )
         SET_SV_2PREDCSRS(
-                      SV_PRED_CSR(1, 2, 0, 0, 10, 1),
-                      SV_PRED_CSR(1, 12, 0, 0, 11, 1) );
+                      SV_PRED_CSR(1, 2, 0, 0, 10, 0),
+                      SV_PRED_CSR(1, 12, 0, 0, 11, 0) );
 
 
   SET_SV_VL(3)

diff --git a/isa/rv64uc/sv_c_mv.S b/isa/rv64uc/sv_c_mv.S
index c85108ce8c548a2ece7836996343760af14ccace..11a042b920aa4fb18efb2b7763bb55d61924b981 100644 (file)
--- a/isa/rv64uc/sv_c_mv.S
+++ b/isa/rv64uc/sv_c_mv.S
@@ -23,8 +23,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         li          x5, 0 # deliberately set x4 to 0
 
         SET_SV_MVL(3)
-        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0),
-                      SV_REG_CSR(1, 6, 0, 6, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1),
+                      SV_REG_CSR(1, 6, 0, 6, 1) )
         SET_SV_VL(3)
 
         .option rvc

diff --git a/isa/rv64uc/sv_c_mv_predication.S b/isa/rv64uc/sv_c_mv_predication.S
index 3ad6535f586584b10151d5eda959632a066241a7..fc0bb7498ba41933cc260819773cd5560442e0aa 100644 (file)
--- a/isa/rv64uc/sv_c_mv_predication.S
+++ b/isa/rv64uc/sv_c_mv_predication.S
@@ -17,11 +17,11 @@ RVTEST_RV64U        # Define TVM used by program.
         li          a4, pred2;                         \
                                                        \
         SET_SV_MVL(3);                                 \
-        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0),    \
-                      SV_REG_CSR(1, 6, 0, 6, 1, 0) );  \
+        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1),       \
+                      SV_REG_CSR(1, 6, 0, 6, 1) );     \
         SET_SV_2PREDCSRS(                              \
-                      SV_PRED_CSR(1, 3, 0, 0, 13, 1),  \
-                      SV_PRED_CSR(1, 6, 0, 0, 14, 1) );\
+                      SV_PRED_CSR(1, 3, 0, 0, 13, 0),  \
+                      SV_PRED_CSR(1, 6, 0, 0, 14, 0) );\
         SET_SV_VL(3);                                  \
                                                        \
         .option rvc;                                   \

diff --git a/isa/rv64uc/sv_c_swsp.S b/isa/rv64uc/sv_c_swsp.S
index c29a9b4a23ae7d67fb839e317adfde8756aa8e03..7990707e7c1ce2ac5a6f7936c3a4d69fa217ac2a 100644 (file)
--- a/isa/rv64uc/sv_c_swsp.S
+++ b/isa/rv64uc/sv_c_swsp.S
@@ -22,8 +22,8 @@ RVTEST_CODE_BEGIN
         li          a4, 1004;
 
         SET_SV_MVL(3)
-        SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1, 0),
-                      SV_REG_CSR(1, 2, 0, 2, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1),
+                      SV_REG_CSR(1, 2, 0, 2, 1) )
         SET_SV_VL(3)
 
   mv a1, sp

diff --git a/isa/rv64ud/sv_fadd.S b/isa/rv64ud/sv_fadd.S
index 9ef208271f6aff174e91e822209dd09bee9bd993..9057dff8e1c2ef531fd871bffb9ef07512a9ee64 100644 (file)
--- a/isa/rv64ud/sv_fadd.S
+++ b/isa/rv64ud/sv_fadd.S
@@ -22,8 +22,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         SV_FLD_DATA( f8, testdata+56, 0)
 
         SET_SV_MVL(2)
-        SET_SV_2CSRS( SV_REG_CSR(0, 2, 0, 2, 1, 0),
-                      SV_REG_CSR(0, 6, 0, 6, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(0, 2, 0, 2, 1),
+                      SV_REG_CSR(0, 6, 0, 6, 1) )
         SET_SV_VL(2)
 
         fadd.d f2, f2, f6;

diff --git a/isa/rv64ui/Makefrag.sv b/isa/rv64ui/Makefrag.sv
index da91e06f75c05d7e301844efd617006c147c0ee9..ab4744da200dcd1a3a1f7d4ed1f21beb158d3cb3 100644 (file)
--- a/isa/rv64ui/Makefrag.sv
+++ b/isa/rv64ui/Makefrag.sv
@@ -8,6 +8,7 @@ rv64ui_sv_tests = \
        sv_addi_scalar_src \
        sv_addi_vector_vector \
        sv_addi_predicated \
+       sv_beq \
 
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sv_tests))
 rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sv_tests))

diff --git a/isa/rv64ui/sv_addi.S b/isa/rv64ui/sv_addi.S
index 123052cf02e1e9e42764f9cef9881783b660d028..b73db85a31c71660265897cc16f018842c04d91f 100644 (file)
--- a/isa/rv64ui/sv_addi.S
+++ b/isa/rv64ui/sv_addi.S
@@ -18,7 +18,7 @@ RVTEST_CODE_BEGIN   # Start of test code.
         SV_LD_DATA( x5, testdata+24, 0)
 
         SET_SV_MVL(2)
-        SET_SV_CSR(1, 3, 0, 3, 1, 0)
+        SET_SV_CSR(1, 3, 0, 3, 1)
         SET_SV_VL(2)
 
         addi    x3, x3, 1

diff --git a/isa/rv64ui/sv_addi_predicated.S b/isa/rv64ui/sv_addi_predicated.S
index 32902f0e4f6aa1fad925f0f3052a31c66e56cc11..46246ea849eb0ebb92077526fc549dc4eaae4af5 100644 (file)
--- a/isa/rv64ui/sv_addi_predicated.S
+++ b/isa/rv64ui/sv_addi_predicated.S
@@ -13,8 +13,8 @@ RVTEST_RV64U        # Define TVM used by program.
         li      x6, pred;                               \
                                                         \
         SET_SV_MVL( 2);                                  \
-        SET_SV_CSR( 1, 3, 0, 3, 1, 0);                   \
-        SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 1);         \
+        SET_SV_CSR( 1, 3, 0, 3, 1);                    \
+        SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 0);         \
         SET_SV_VL( 2);                                   \
                                                         \
         addi    x3, x3, 1;                              \

diff --git a/isa/rv64ui/sv_addi_redirect.S b/isa/rv64ui/sv_addi_redirect.S
index 61e92842147e295fc91295caa98997e06a3d9cb3..74d41e0c57d32886266a36daa082cbe02ea520e0 100644 (file)
--- a/isa/rv64ui/sv_addi_redirect.S
+++ b/isa/rv64ui/sv_addi_redirect.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN   # Start of test code.
         SV_LD_DATA( x5, testdata+24, 0)
 
         SET_SV_MVL(2)
-        SET_SV_CSR(1, 16, 0, 3, 1, 0)
+        SET_SV_CSR(1, 16, 0, 3, 1)
         SET_SV_VL(2)
 
         addi    x16, x16, 1

diff --git a/isa/rv64ui/sv_addi_scalar_src.S b/isa/rv64ui/sv_addi_scalar_src.S
index 182b2ae19eeab86f5693cc907ab5ec5239e488ad..e17df23dc92cfca61a2ff0a43b91c97a34e91955 100644 (file)
--- a/isa/rv64ui/sv_addi_scalar_src.S
+++ b/isa/rv64ui/sv_addi_scalar_src.S
@@ -21,7 +21,7 @@ RVTEST_CODE_BEGIN   # Start of test code.
         li x6, 41 # going to be stored in x3 *and* x4 (plus one, on each)
 
         SET_SV_MVL(2)
-        SET_SV_CSR(1, 3, 0, 3, 1, 0)
+        SET_SV_CSR(1, 3, 0, 3, 1)
         SET_SV_VL(2)
 
         addi    x3, x6, 1 # x3 = x6+1 *AND* x4 = x6+1

diff --git a/isa/rv64ui/sv_addi_vector_vector.S b/isa/rv64ui/sv_addi_vector_vector.S
index ea1f3c638112b1122d594eb12f601f04898ccf36..8594ba7566f38efe007411888f50862eee5c6d60 100644 (file)
--- a/isa/rv64ui/sv_addi_vector_vector.S
+++ b/isa/rv64ui/sv_addi_vector_vector.S
@@ -21,8 +21,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         li          x4, 0 # deliberately set x4 to 0
 
         SET_SV_MVL(2)
-        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0),
-                      SV_REG_CSR(1, 6, 0, 6, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1),
+                      SV_REG_CSR(1, 6, 0, 6, 1) )
         SET_SV_VL(2)
 
         addi    x3, x6, 1