isa/rv64ui/sv_addi_redirect.S

   1 #include "riscv_test.h"
   2 #include "sv_test_macros.h"
   3
   4 RVTEST_RV64U        # Define TVM used by program.
   5
   6 # SV test: vector-vector (redirected) add
   7 #
   8 # sets up x3 and x4 with data, then sets up SV redirection
   9 # from register x16 to register x3 with a VL of 2.  the add is carried out
  10 # on x16 and the redirection means "actually, we want to do that add on x3"
  11 # and the VL means "actually we want to do that add on x3 *AND* x4"
  12 # x2 and x5 are tested to make sure they're not modified
  13
  14 # Test code region.
  15 RVTEST_CODE_BEGIN   # Start of test code.
  16
  17         SV_LD_DATA( x2, testdata   , 0)
  18         SV_LD_DATA( x3, testdata+8 , 0)
  19         SV_LD_DATA( x4, testdata+16, 0)
  20         SV_LD_DATA( x5, testdata+24, 0)
  21
  22         SET_SV_MVL(2)
  23         SET_SV_CSR(1, 16, 0, 3, 1)
  24         SET_SV_VL(2)
  25
  26         addi    x16, x16, 1
  27
  28         CLR_SV_CSRS()
  29         SET_SV_VL(0)
  30         SET_SV_MVL(0)
  31
  32         TEST_SV_IMM(x2, 1001) # should not be modified
  33         TEST_SV_IMM(x3, 42)
  34         TEST_SV_IMM(x4, 43)
  35         TEST_SV_IMM(x5, 1002) # should not be modified
  36
  37         RVTEST_PASS           # Signal success.
  38 fail:
  39         RVTEST_FAIL
  40 RVTEST_CODE_END     # End of test code.
  41
  42 # Input data section.
  43 # This section is optional, and this data is NOT saved in the output.
  44 .data
  45         .align 3
  46 testdata:
  47         .dword 1001
  48         .dword 41
  49         .dword 42
  50         .dword 1002
  51
  52 # Output data section.
  53 RVTEST_DATA_BEGIN   # Start of test output data region.
  54         .align 3
  55 result:
  56         .dword -1
  57         .dword -1
  58         .dword -1
  59 RVTEST_DATA_END     # End of test output data region.
  60