isa/rv64ui/sv_addi_predicated.S

   1 #include "riscv_test.h"
   2 #include "sv_test_macros.h"
   3
   4 RVTEST_RV64U        # Define TVM used by program.
   5
   6 #define SV_PREDICATION_TEST( pred, inv, zero, expect1, expect2 ) \
   7                                                         \
   8         SV_LD_DATA( x2, testdata   , 0);               \
   9         SV_LD_DATA( x3, testdata+8 , 0);               \
  10         SV_LD_DATA( x4, testdata+16, 0);               \
  11         SV_LD_DATA( x5, testdata+24, 0);               \
  12                                                         \
  13         li      x6, pred;                               \
  14                                                         \
  15         SET_SV_MVL( 2);                                  \
  16         SET_SV_CSR( 1, 3, 0, 3, 1, 0);                   \
  17         SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 1);         \
  18         SET_SV_VL( 2);                                   \
  19                                                         \
  20         addi    x3, x3, 1;                              \
  21                                                         \
  22         CLR_SV_CSRS();                                  \
  23         SET_SV_VL( 0);                                   \
  24         SET_SV_MVL( 0);                                  \
  25                                                         \
  26         TEST_SV_IMM( x2, 1001);                         \
  27         TEST_SV_IMM( x3, expect1);                       \
  28         TEST_SV_IMM( x4, expect2);                       \
  29         TEST_SV_IMM( x5, 1002);
  30
  31
  32 # SV test: vector-vector add
  33 #
  34 # sets up x3 and x4 with data, sets VL to 2, and carries out
  35 # an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
  36
  37 # Test code region.
  38 RVTEST_CODE_BEGIN   # Start of test code.
  39
  40         # no zeroing, no inversion
  41         SV_PREDICATION_TEST( 0x1, 0, 0, 42, 42 )
  42         SV_PREDICATION_TEST( 0x2, 0, 0, 41, 43 )
  43         SV_PREDICATION_TEST( 0x3, 0, 0, 42, 43 )
  44         SV_PREDICATION_TEST( 0x0, 0, 0, 41, 42 )
  45
  46         # zeroing, no inversion
  47         SV_PREDICATION_TEST( 0x1, 0, 1, 42, 0 )
  48         SV_PREDICATION_TEST( 0x2, 0, 1, 0, 43 )
  49         SV_PREDICATION_TEST( 0x3, 0, 1, 42, 43 )
  50         SV_PREDICATION_TEST( 0x0, 0, 1, 0, 0 )
  51
  52         # no zeroing, inversion
  53         SV_PREDICATION_TEST( 0x2, 1, 0, 42, 42 )
  54         SV_PREDICATION_TEST( 0x1, 1, 0, 41, 43 )
  55         SV_PREDICATION_TEST( 0x0, 1, 0, 42, 43 )
  56         SV_PREDICATION_TEST( 0x3, 1, 0, 41, 42 )
  57
  58         # zeroing, inversion
  59         SV_PREDICATION_TEST( 0x2, 1, 1, 42, 0 )
  60         SV_PREDICATION_TEST( 0x1, 1, 1, 0, 43 )
  61         SV_PREDICATION_TEST( 0x0, 1, 1, 42, 43 )
  62         SV_PREDICATION_TEST( 0x3, 1, 1, 0, 0 )
  63
  64         RVTEST_PASS           # Signal success.
  65 fail:
  66         RVTEST_FAIL
  67 RVTEST_CODE_END     # End of test code.
  68
  69 # Input data section.
  70 # This section is optional, and this data is NOT saved in the output.
  71 .data
  72         .align 3
  73 testdata:
  74         .dword 1001
  75         .dword 41
  76         .dword 42
  77         .dword 1002
  78
  79 # Output data section.
  80 RVTEST_DATA_BEGIN   # Start of test output data region.
  81         .align 3
  82 result:
  83         .dword -1
  84         .dword -1
  85         .dword -1
  86 RVTEST_DATA_END     # End of test output data region.
  87