add cleanup and comments to sv lwsp pred test

diff --git a/isa/rv64uc/sv_c_lwsp_predication.S b/isa/rv64uc/sv_c_lwsp_predication.S
index 69afdc5dc8060b1467bf0539f373433eab5de20c..d2caf8be6768d04661cd764e900e4dfab0b7a1ce 100644 (file)
--- a/isa/rv64uc/sv_c_lwsp_predication.S
+++ b/isa/rv64uc/sv_c_lwsp_predication.S
@@ -1,10 +1,10 @@
 # See LICENSE for license details.
 
 #*****************************************************************************
-# rvc.S
+# sv_c_lwsp_predication.S
 #-----------------------------------------------------------------------------
 #
-# Test RVC corner cases.
+# Test RVC c.lwsp with twin-predication.
 #
 
 #include "riscv_test.h"
@@ -17,11 +17,11 @@ RVTEST_CODE_BEGIN
   .option push
   .option norvc
 
-        li          a2, 0 
-        li          a3, 0 
-        li          a4, 0 
+        li          a2, 0
+        li          a3, 0
+        li          a4, 0
         li          a0, 0x6; // targetted by use of sp: means skip, copy, copy
-        li          a1, 0x5; // targetted by use of a2: meanss a2, x, a4
+        li          a1, 0x5; // targetted by use of a2: meanss a2, skip, a4
 
 
   mv a6, sp
@@ -31,15 +31,15 @@ RVTEST_CODE_BEGIN
         SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1, 0),
                       SV_REG_CSR(1, 2, 0, 2, 1, 0) )
         SET_SV_2PREDCSRS(
-                      SV_PRED_CSR(1, 2, 0, 0, 10, 1),  
+                      SV_PRED_CSR(1, 2, 0, 0, 10, 1),
                       SV_PRED_CSR(1, 12, 0, 0, 11, 1) );
 
 
   SET_SV_VL(3)
 
   .option push;
-  .option rvc; 
-  .align 2; 
+  .option rvc;
+  .align 2;
   c.lwsp a2, 0(sp); # actually lw a2, 4(sp); lw a4 8(sp) due to twin-predication
   #lw a2, 0(sp);
   .option pop
@@ -51,8 +51,8 @@ RVTEST_CODE_BEGIN
 
   mv sp, a6
 
-        TEST_SV_IMM(a2, 1002) 
-        TEST_SV_IMM(a3, 0)
+        TEST_SV_IMM(a2, 1002) # data[0] was skipped (a0 & 1 == 0)
+        TEST_SV_IMM(a3, 0)    # a3 was skipped (a1 & 2 == 0)
         TEST_SV_IMM(a4, 1005)
 
   .option pop