projects / riscv-tests.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: ee5c8e9) | patch
add sv addi predicated unit test, including inversion and zeroing
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 1 Oct 2018 13:41:45 +0000 (14:41 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 1 Oct 2018 13:41:45 +0000 (14:41 +0100)
commitc4390e4f843d17d211d6723b2c1ec83e0b217a00
tree096b6db4ece1546b21ea4fcf54482d05505868b3tree
parentee5c8e9acfbbcf47cf131612dcc384975b399d2dcommit | diff
add sv addi predicated unit test, including inversion and zeroing
isa/macros/simplev/sv_test_macros.h diff | blob | history
isa/rv64ui/Makefrag.sv diff | blob | history
isa/rv64ui/sv_addi_predicated.S [new file with mode: 0644] blob