add sv addi predicated unit test, including inversion and zeroing

[riscv-tests.git] / isa / macros / simplev / sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index d77287403e2c96b1a2b4c2c14773bed78751a4d4..22eb2b17db9d5e893856165c12c91f68176f15cd 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -8,7 +8,12 @@
         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ); \
         csrrw  x0, 0x4c0, x1
 
+#define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
+        li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, active ); \
+        csrrw  x0, 0x4c8, x1
+
 #define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
+#define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
 
 #define SET_SV_MVL( val ) csrrwi   x0, 0x4f2, val
 #define SET_SV_VL( val )  csrrwi   x0, 0x4f0, val