Update pre-launch page with Kazan details and logo

[crowdsupply.git] / markdown / pre-launch.md

diff --git a/markdown/pre-launch.md b/markdown/pre-launch.md
index c01ea02b055880209da0af6d59e7fdd0ab0358b3..a440104ac1e9a58fb8695a61c5b5ae070b9c131a 100644 (file)
--- a/markdown/pre-launch.md
+++ b/markdown/pre-launch.md
@@ -9,16 +9,18 @@ embedded systems. Full source code and files are available not only
 for the operating system and bootloader, but also for the processor,
 its peripherals and its 3D GPU and VPU.
 
 for the operating system and bootloader, but also for the processor,
 its peripherals and its 3D GPU and VPU.
 

+{kazan-logo}
+

 Onboard the Libre RISC-V M-Class is the
 [Kazan](https://salsa.debian.org/Kazan-team/kazan) GPU, a
 Onboard the Libre RISC-V M-Class is the
 [Kazan](https://salsa.debian.org/Kazan-team/kazan) GPU, a

-libre-licensed software-rendered
+libre-licensed, software-rendered

 [Vulkan](https://www.khronos.org/vulkan/) Driver written in
 [Vulkan](https://www.khronos.org/vulkan/) Driver written in

-Rust that uses LLVM for code generation.  Kazan will use Optimised 3D
-instructions specifically designed and added to the Libre RISC-V M-Class
+Rust that uses LLVM for code generation.  Kazan will use optimised 3D
+instructions specifically designed for and added to the Libre RISC-V M-Class

 SoC, yet Kazan itself may still be used (unoptimised) on other hardware.
 
 SoC, yet Kazan itself may still be used (unoptimised) on other hardware.
 

-The performance target for Kazan on the Libre RISCV SoC is a very modest
-mobile-class level (1280x720 25fps, 100MPixels/sec, 30MTriangles/sec,
-5-6GFLOPs), whilst the power budget is very tight: under 2.5 watts in 28nm.
-With RISC-V being 40% more power efficient than x86 or ARM, this is
-very reasonably achievable.
+The performance target for Kazan on the Libre RISCV SoC is a very
+modest mobile-class level (1280 x 720 25 fps, 100 Mpixels/sec, 30
+Mtriangles/sec, 5-6 GFLOPs), whilst the power budget is very tight
+(under 2.5 watts in a 28 nm process).  With RISC-V being 40% more
+power efficient than x86 or ARM, this is very reasonably achievable.