-* The GPU is integrated (like Mali400). So all that the GPU needs to do
- is write to an area of memory (framebuffer or area of the framebuffer).
- the SoC - which in this case has a RISC-V core and has peripherals such
- as the LCD controller - will take care of the rest.
-* In this arcitecture, the GPU, the CPU and the peripherals are all on
- the same AXI4 shared memory bus. They all have access to the same shared
- DDR3/DDR4 RAM. So as a result the GPU will use AXI4 to write directly
- to the framebuffer and the rest will be handle by SoC.
-* The job must be done by a team that shows sufficient expertise to
- reduce the risk. (Do you mean a team with good CVs? What about if the
- team shows you an acceptable FPGA prototype? I’m talking about a team
- of students which do not have big industrial CVs but they know how to
- handle this job (just like RocketChip or MIAOW or etc…).
+* The GPU is integrated (like Mali-400). So all that the GPU needs to do is write to an area of memory (framebuffer or area of the framebuffer). The SoC - which in this case has a RISC-V core and has peripherals such as the LCD controller - will take care of the rest.
+* In this arcitecture, the GPU, the CPU and the peripherals are all on the same AXI4 shared memory bus. They all have access to the same shared DDR3/DDR4 RAM. So as a result the GPU will use AXI4 to write directly to the framebuffer and the rest will be handle by SoC.
+* The job must be done by a team that shows sufficient expertise to reduce the risk.
+
+## Notes
+
+* The deadline is really tight. If an FPGA (or simulation) plus the basics of the software driver are at least prototyped by then it *might* be ok.
+* If using Nyuzi as the basis it *might* be possible to begin the software port in parallel because Jeff went to the trouble of writing a cycle-accurate simulation.
+* I *suspect* it will result in less work to use Gallium3D than, for example, writing an entire OpenGL stack from scratch.
+* A *demo* should run on an FPGA as an initial. The FPGA is not a priority for assessment, but it would be *nice* if
+it could fit into a ZC706.
+* Also if there is parallel hardware obviously it would be nice to be able to demonstrate parallelism to the maximum extend possible. But again, being reasonable, if the GPU is so big that only a single core can fit into even a large FPGA then for an initial demo that would be fine.
+* Note that no other licenses are acceptable. GPLv2+ is out.
+
+## Design decisions and considerations
+
+Whilst Nyuzi has a big advantage in that it has simuations and also a llvm port and so on, if utilised for this particular RISC-V chip it would mean needing to write a "memory shim" between the general-purpose Nyuzi core and the main processor, i.e. all the shader info, state etc. needs synchronisation hardware (and software). That could significantly complicate design, especially of software.
+
+Whilst i *recommended* Gallium3D there is actually another possible approach:
+
+A RISC-V multi-core design which accelerates *software* rendering... including potentially utilising the fact that Gallium3D has a *software* (LLVM) renderer:
+
+<https://mesa3d.org/llvmpipe.html>
+
+The general aim of this approach is *not* to have the complexity of transferring significant amounts of data structures to and from disparate cores (one Nyuzi, one RISC-V) but to STAY WITHIN THE RISC-V ARCHITECTURE and simply compile Mesa3D (for RISC-V), gallium3d-llvm (for RISC-V), modifying llvm for RISC-V to do the heavy-lifting instead.
+
+Then it just becomes a matter of adding Vector/SIMD/Parallelization extensions to RISC-V, and adding support in LLVM for the same:
+
+<https://lists.llvm.org/pipermail/llvm-dev/2018-April/122517.html>
+
+So if considering to base the design on RISC-V, that means turning RISC-V into a vector processor. Now, whilst Hwacha has been located (finally), it's a design that is specifically targetted at supercomputers. I have been taking an alternative approach to vectorisation which is more about *parallelization* than it is about *vectorization*.
+
+It would be great for Simple-V to be given consideration for implementation as the abstraction "API" of Simple-V would greatly simplify the addition process of Custom features such as fixed-function pixel conversion and rasterization instructions (if those are chosen to be added) and so on. Bear in mind that a high-speed clock rate is NOT a good idea for GPUs (power being a square law), multi-core parallelism and longer SIMD/vectors are much better to consider, instead.
+
+The PDF/slides on Simple-V is here:
+
+<http://hands.com/~lkcl/simple_v_chennai_2018.pdf>
+
+And the assessment, design and implementation is being done here:
+
+<http://libre-riscv.org/simple_v_extension/>