-the general aim of this approach is *not* to have the complexity of
-transferring significant amounts of data structures to and from disparate
-cores (one Nyuzi, one RISC-V) but to STAY WITHIN THE RISC-V ARCHITECTURE
-and simply compile mesa3d (for RISC-V), gallium3d-llvm (for RISC-V).
-
-so if considering to base the design on RISC-V, that means turning RISC-V
-into a vector processor. now, whilst hwacha has been located (finally),
-it's a design that is specifically targetted at supercomputers. i have
-been taking an alternative approach to vectorisation which is more about
-*parallelisation* than it is about *vectorisation*.
-
-it would be great for Simple-V to be given consideration for
-implementation as the abstraction "API" of Simple-V would greatly simplify
-the addition process of Custom features such as fixed-function pixel
-conversion and rasterisation instructions (if those are chosen to be
-added) and so on. bear in mind that a high-speed clock rate is NOT a
-good idea for GPUs (power being a square law), multi-core parallelism
-and longer SIMD/vectors are much better to consider, instead.
-
-the PDF / slides on Simple-V is here:
-<http://hands.com/~lkcl/simple_v_chennai_2018.pdf>