+ # select immediate if opcode says so. however also change the latch
+ # to trigger *from* the opcode latch instead.
+ src2_or_imm = Signal(self.rwid, reset_less=True)
+ src_sel = Signal(reset_less=True)
+ m.d.comb += src_sel.eq(Mux(op_is_imm, opc_l.qn, src_l.q))
+ m.d.comb += src2_or_imm.eq(Mux(op_is_imm, self.imm_i, self.src2_i))
+
+ # create a latch/register for src1/src2
+ latchregister(m, self.src1_i, self.alu.a, src_l.q)
+ latchregister(m, src2_or_imm, self.alu.b, src_sel)
+
+ # -----
+ # outputs
+ # -----
+
+ # all request signals gated by busy_o. prevents picker problems
+ busy_o = self.busy_o
+ m.d.comb += busy_o.eq(opc_l.q) # busy out
+ m.d.comb += self.rd_rel_o.eq(src_l.q & busy_o) # src1/src2 req rel
+
+ # the counter is just for demo purposes, to get the ALUs of different
+ # types to take arbitrary completion times
+ with m.If(opc_l.qn):
+ m.d.sync += self.counter.eq(0)
+ with m.If(req_l.qn & busy_o & (self.counter == 0)):
+ with m.If(self.alu.op == 2): # MUL, to take 5 instructions
+ m.d.sync += self.counter.eq(5)
+ with m.Elif(self.alu.op == 3): # SHIFT to take 7
+ m.d.sync += self.counter.eq(7)
+ with m.Elif(self.alu.op >= 4): # Branches take 6 (to test shadow)
+ m.d.sync += self.counter.eq(6)
+ with m.Else(): # ADD/SUB to take 2
+ m.d.sync += self.counter.eq(2)
+ with m.If(self.counter > 1):
+ m.d.sync += self.counter.eq(self.counter - 1)
+ with m.If(self.counter == 1):
+ # write req release out. waits until shadow is dropped.
+ m.d.comb += self.req_rel_o.eq(req_l.q & busy_o & self.shadown_i)