- latchregister(m, self.alu.o, data_r, req_l.q)
-
- with m.If(self.go_wr_i):
- m.d.comb += self.data_o.eq(data_r)
+ latchregister(m, self.alu.o, data_r, alulatch)
+
+ # decode bits of operand (latched)
+ comb += op_alu.eq(oper_r[0])
+ comb += op_is_imm.eq(oper_r[1])
+ comb += op_is_ld.eq(oper_r[2])
+ comb += op_is_st.eq(oper_r[3])
+ comb += op_ldst.eq(op_is_ld | op_is_st)
+ comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
+ comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
+
+ # on a go_read, tell the ALU we're accepting data.
+ # NOTE: this spells TROUBLE if the ALU isn't ready!
+ # go_read is only valid for one clock!
+ with m.If(self.go_rd_i): # src operands ready, GO!
+ with m.If(~self.alu.p_ready_o): # no ACK yet
+ m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
+
+ # put the register directly onto the output
+ comb += self.data_o.eq(data_r)