+ """ LOAD / STORE / ADD / SUB Computation Unit
+
+ Inputs
+ ------
+
+ * :rwid: register width
+ * :alu: an ALU module
+ * :mem: a Memory Module (read-write capable)
+
+ Control Signals (In)
+ --------------------
+
+ * :issue_i: LD/ST is being "issued".
+ * :isalu_i: ADD/SUB is being "issued" (aka issue_alu_i)
+ * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
+ * :go_rd_i: read is being actioned (latches in src regs)
+ * :go_ad_i: address is being actioned (triggers actual mem LD)
+ * :go_st_i: store is being actioned (triggers actual mem STORE)
+ * :go_die_i: resets the unit back to "wait for issue"
+ """