+ with m.Elif((op & (0x3<<4)) != 0): # ld/st
+ # see compldst.py
+ # bit 0: ADD/SUB
+ # bit 1: immed
+ # bit 4: LD
+ # bit 5: ST
+ comb += sc.ls_oper_i.eq(Cat(op[0], opi[0], op[4:6]))
+ comb += sc.ls_imm_i.eq(imm)
+ comb += sc.lsissue.insn_i.eq(1)
+ comb += wait_issue_ls.eq(1)
+ with m.Else(): # alu