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remove unneeded signals
[soc.git]
/
src
/
experiment
/
score6600.py
diff --git
a/src/experiment/score6600.py
b/src/experiment/score6600.py
index 47101d1e90f68b6ab4fa15308a53349bcf1c0ad8..7c66f208c52d2f72828450564ef129e1ed299e95 100644
(file)
--- a/
src/experiment/score6600.py
+++ b/
src/experiment/score6600.py
@@
-181,6
+181,7
@@
class CompUnitALUs(CompUnitsBase):
# inputs
self.oper_i = Signal(opwid, reset_less=True)
# inputs
self.oper_i = Signal(opwid, reset_less=True)
+ self.imm_i = Signal(rwid, reset_less=True)
# Int ALUs
add = ALU(rwid)
# Int ALUs
add = ALU(rwid)
@@
-190,7
+191,8
@@
class CompUnitALUs(CompUnitsBase):
units = []
for alu in [add, sub, mul, shf]:
units = []
for alu in [add, sub, mul, shf]:
- units.append(ComputationUnitNoDelay(rwid, 2, alu))
+ aluopwid = 3 # extra bit for immediate mode
+ units.append(ComputationUnitNoDelay(rwid, aluopwid, alu))
CompUnitsBase.__init__(self, rwid, units)
CompUnitsBase.__init__(self, rwid, units)
@@
-198,9
+200,10
@@
class CompUnitALUs(CompUnitsBase):
m = CompUnitsBase.elaborate(self, platform)
comb = m.d.comb
m = CompUnitsBase.elaborate(self, platform)
comb = m.d.comb
- # hand the same operation to all units
+ # hand the same operation to all units
, only lower 2 bits though
for alu in self.units:
for alu in self.units:
- comb += alu.oper_i.eq(self.oper_i)
+ comb += alu.oper_i[0:3].eq(self.oper_i)
+ comb += alu.imm_i.eq(self.imm_i)
return m
return m
@@
-220,10
+223,12
@@
class CompUnitBR(CompUnitsBase):
# inputs
self.oper_i = Signal(opwid, reset_less=True)
# inputs
self.oper_i = Signal(opwid, reset_less=True)
+ self.imm_i = Signal(rwid, reset_less=True)
# Branch ALU and CU
self.bgt = BranchALU(rwid)
# Branch ALU and CU
self.bgt = BranchALU(rwid)
- self.br1 = ComputationUnitNoDelay(rwid, 3, self.bgt)
+ aluopwid = 3 # extra bit for immediate mode
+ self.br1 = ComputationUnitNoDelay(rwid, aluopwid, self.bgt)
CompUnitsBase.__init__(self, rwid, [self.br1])
def elaborate(self, platform):
CompUnitsBase.__init__(self, rwid, [self.br1])
def elaborate(self, platform):
@@
-233,6
+238,7
@@
class CompUnitBR(CompUnitsBase):
# hand the same operation to all units
for alu in self.units:
comb += alu.oper_i.eq(self.oper_i)
# hand the same operation to all units
for alu in self.units:
comb += alu.oper_i.eq(self.oper_i)
+ comb += alu.imm_i.eq(self.imm_i)
return m
return m
@@
-254,14
+260,12
@@
class FunctionUnits(Elaboratable):
self.src1_rsel_o = Signal(n_regs, reset_less=True) # src1 reg (bot)
self.src2_rsel_o = Signal(n_regs, reset_less=True) # src2 reg (bot)
self.src1_rsel_o = Signal(n_regs, reset_less=True) # src1 reg (bot)
self.src2_rsel_o = Signal(n_regs, reset_less=True) # src2 reg (bot)
- self.req_rel_i = Signal(n_int_alus, reset_less = True)
self.readable_o = Signal(n_int_alus, reset_less=True)
self.writable_o = Signal(n_int_alus, reset_less=True)
self.go_rd_i = Signal(n_int_alus, reset_less=True)
self.go_wr_i = Signal(n_int_alus, reset_less=True)
self.go_die_i = Signal(n_int_alus, reset_less=True)
self.readable_o = Signal(n_int_alus, reset_less=True)
self.writable_o = Signal(n_int_alus, reset_less=True)
self.go_rd_i = Signal(n_int_alus, reset_less=True)
self.go_wr_i = Signal(n_int_alus, reset_less=True)
self.go_die_i = Signal(n_int_alus, reset_less=True)
- self.req_rel_o = Signal(n_int_alus, reset_less=True)
self.fn_issue_i = Signal(n_int_alus, reset_less=True)
# Note: FURegs wr_pend_o is also outputted from here, for use in WaWGrid
self.fn_issue_i = Signal(n_int_alus, reset_less=True)
# Note: FURegs wr_pend_o is also outputted from here, for use in WaWGrid
@@
-277,14
+281,14
@@
class FunctionUnits(Elaboratable):
intfudeps = FUFUDepMatrix(n_intfus, n_intfus)
m.submodules.intfudeps = intfudeps
# Integer FU-Reg Dep Matrix
intfudeps = FUFUDepMatrix(n_intfus, n_intfus)
m.submodules.intfudeps = intfudeps
# Integer FU-Reg Dep Matrix
- intregdeps = FURegDepMatrix(n_intfus, self.n_regs)
+ intregdeps = FURegDepMatrix(n_intfus, self.n_regs
, 2
)
m.submodules.intregdeps = intregdeps
m.submodules.intregdeps = intregdeps
- comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o)
- comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o)
+ comb += self.g_int_rd_pend_o.eq(intregdeps.
v_
rd_rsel_o)
+ comb += self.g_int_wr_pend_o.eq(intregdeps.
v_
wr_rsel_o)
- comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o)
- comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o)
+ comb += intregdeps.rd_pend_i.eq(intregdeps.
v_
rd_rsel_o)
+ comb += intregdeps.wr_pend_i.eq(intregdeps.
v_
wr_rsel_o)
comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o)
comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o)
comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o)
comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o)
@@
-299,8
+303,8
@@
class FunctionUnits(Elaboratable):
# Connect function issue / arrays, and dest/src1/src2
comb += intregdeps.dest_i.eq(self.dest_i)
# Connect function issue / arrays, and dest/src1/src2
comb += intregdeps.dest_i.eq(self.dest_i)
- comb += intregdeps.src
1_i
.eq(self.src1_i)
- comb += intregdeps.src
2_i
.eq(self.src2_i)
+ comb += intregdeps.src
_i[0]
.eq(self.src1_i)
+ comb += intregdeps.src
_i[1]
.eq(self.src2_i)
comb += intregdeps.go_rd_i.eq(self.go_rd_i)
comb += intregdeps.go_wr_i.eq(self.go_wr_i)
comb += intregdeps.go_rd_i.eq(self.go_rd_i)
comb += intregdeps.go_wr_i.eq(self.go_wr_i)
@@
-308,8
+312,8
@@
class FunctionUnits(Elaboratable):
comb += intregdeps.issue_i.eq(self.fn_issue_i)
comb += self.dest_rsel_o.eq(intregdeps.dest_rsel_o)
comb += intregdeps.issue_i.eq(self.fn_issue_i)
comb += self.dest_rsel_o.eq(intregdeps.dest_rsel_o)
- comb += self.src1_rsel_o.eq(intregdeps.src
1_rsel_o
)
- comb += self.src2_rsel_o.eq(intregdeps.src
2_rsel_o
)
+ comb += self.src1_rsel_o.eq(intregdeps.src
_rsel_o[0]
)
+ comb += self.src2_rsel_o.eq(intregdeps.src
_rsel_o[1]
)
return m
return m
@@
-333,7
+337,9
@@
class Scoreboard(Elaboratable):
self.brissue = IssueUnitGroup(1)
# and these
self.alu_oper_i = Signal(4, reset_less=True)
self.brissue = IssueUnitGroup(1)
# and these
self.alu_oper_i = Signal(4, reset_less=True)
+ self.alu_imm_i = Signal(rwid, reset_less=True)
self.br_oper_i = Signal(4, reset_less=True)
self.br_oper_i = Signal(4, reset_less=True)
+ self.br_imm_i = Signal(rwid, reset_less=True)
# inputs
self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
# inputs
self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
@@
-372,8
+378,8
@@
class Scoreboard(Elaboratable):
# Int ALUs and Comp Units
n_int_alus = 5
# Int ALUs and Comp Units
n_int_alus = 5
- cua = CompUnitALUs(self.rwid,
2
)
- cub = CompUnitBR(self.rwid,
2
)
+ cua = CompUnitALUs(self.rwid,
3
)
+ cub = CompUnitBR(self.rwid,
3
)
m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub])
bgt = cub.bgt # get at the branch computation unit
br1 = cub.br1
m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub])
bgt = cub.bgt # get at the branch computation unit
br1 = cub.br1
@@
-427,7
+433,9
@@
class Scoreboard(Elaboratable):
# take these to outside (issue needs them)
comb += cua.oper_i.eq(self.alu_oper_i)
# take these to outside (issue needs them)
comb += cua.oper_i.eq(self.alu_oper_i)
+ comb += cua.imm_i.eq(self.alu_imm_i)
comb += cub.oper_i.eq(self.br_oper_i)
comb += cub.oper_i.eq(self.br_oper_i)
+ comb += cub.imm_i.eq(self.br_imm_i)
# TODO: issueunit.f (FP)
# TODO: issueunit.f (FP)
@@
-649,10
+657,12
@@
class IssueToScoreboard(Elaboratable):
# "resetting" done above (insn_i=0) could be re-ASSERTed.
with m.If(iq.qlen_o != 0):
# get the operands and operation
# "resetting" done above (insn_i=0) could be re-ASSERTed.
with m.If(iq.qlen_o != 0):
# get the operands and operation
+ imm = iq.data_o[0].imm_i
dest = iq.data_o[0].dest_i
src1 = iq.data_o[0].src1_i
src2 = iq.data_o[0].src2_i
op = iq.data_o[0].oper_i
dest = iq.data_o[0].dest_i
src1 = iq.data_o[0].src1_i
src2 = iq.data_o[0].src2_i
op = iq.data_o[0].oper_i
+ opi = iq.data_o[0].opim_i # immediate set
# set the src/dest regs
comb += sc.int_dest_i.eq(dest)
# set the src/dest regs
comb += sc.int_dest_i.eq(dest)
@@
-663,11
+673,13
@@
class IssueToScoreboard(Elaboratable):
# choose a Function-Unit-Group
with m.If((op & (0x3<<2)) != 0): # branch
comb += sc.brissue.insn_i.eq(1)
# choose a Function-Unit-Group
with m.If((op & (0x3<<2)) != 0): # branch
comb += sc.brissue.insn_i.eq(1)
- comb += sc.br_oper_i.eq(op & 0x3)
+ comb += sc.br_oper_i.eq(Cat(op[0:2], opi))
+ comb += sc.br_imm_i.eq(imm)
comb += wait_issue_br.eq(1)
with m.Else(): # alu
comb += sc.aluissue.insn_i.eq(1)
comb += wait_issue_br.eq(1)
with m.Else(): # alu
comb += sc.aluissue.insn_i.eq(1)
- comb += sc.alu_oper_i.eq(op & 0x3)
+ comb += sc.alu_oper_i.eq(Cat(op[0:2], opi))
+ comb += sc.alu_imm_i.eq(imm)
comb += wait_issue_alu.eq(1)
# XXX TODO
comb += wait_issue_alu.eq(1)
# XXX TODO
@@
-703,10
+715,12
@@
class RegSim:
self.rwidth = rwidth
self.regs = [0] * nregs
self.rwidth = rwidth
self.regs = [0] * nregs
- def op(self, op, op_imm, src1, src2, dest):
+ def op(self, op, op_imm,
imm,
src1, src2, dest):
maxbits = (1 << self.rwidth) - 1
src1 = self.regs[src1] & maxbits
maxbits = (1 << self.rwidth) - 1
src1 = self.regs[src1] & maxbits
- if not op_imm: # put op in src2
+ if op_imm:
+ src2 = imm
+ else:
src2 = self.regs[src2] & maxbits
if op == IADD:
val = src1 + src2
src2 = self.regs[src2] & maxbits
if op == IADD:
val = src1 + src2
@@
-746,8
+760,9
@@
class RegSim:
yield from self.dump(dut)
assert False
yield from self.dump(dut)
assert False
-def instr_q(dut, op, op_imm, src1, src2, dest, branch_success, branch_fail):
- instrs = [{'oper_i': op, 'dest_i': dest, 'opim_i': op_imm,
+def instr_q(dut, op, op_imm, imm, src1, src2, dest,
+ branch_success, branch_fail):
+ instrs = [{'oper_i': op, 'dest_i': dest, 'imm_i': imm, 'opim_i': op_imm,
'src1_i': src1, 'src2_i': src2}]
sendlen = 1
'src1_i': src1, 'src2_i': src2}]
sendlen = 1
@@
-765,7
+780,7
@@
def instr_q(dut, op, op_imm, src1, src2, dest, branch_success, branch_fail):
yield dut.p_add_i.eq(0)
yield dut.p_add_i.eq(0)
-def int_instr(dut, op, src1, src2, dest, branch_success, branch_fail):
+def int_instr(dut, op,
imm,
src1, src2, dest, branch_success, branch_fail):
yield from disable_issue(dut)
yield dut.int_dest_i.eq(dest)
yield dut.int_src1_i.eq(src1)
yield from disable_issue(dut)
yield dut.int_dest_i.eq(dest)
yield dut.int_src1_i.eq(src1)
@@
-773,10
+788,12
@@
def int_instr(dut, op, src1, src2, dest, branch_success, branch_fail):
if (op & (0x3<<2)) != 0: # branch
yield dut.brissue.insn_i.eq(1)
yield dut.br_oper_i.eq(Const(op & 0x3, 2))
if (op & (0x3<<2)) != 0: # branch
yield dut.brissue.insn_i.eq(1)
yield dut.br_oper_i.eq(Const(op & 0x3, 2))
+ yield dut.br_imm_i.eq(imm)
dut_issue = dut.brissue
else:
yield dut.aluissue.insn_i.eq(1)
yield dut.alu_oper_i.eq(Const(op & 0x3, 2))
dut_issue = dut.brissue
else:
yield dut.aluissue.insn_i.eq(1)
yield dut.alu_oper_i.eq(Const(op & 0x3, 2))
+ yield dut.alu_imm_i.eq(imm)
dut_issue = dut.aluissue
yield dut.reg_enable_i.eq(1)
dut_issue = dut.aluissue
yield dut.reg_enable_i.eq(1)
@@
-803,14
+820,15
@@
def create_random_ops(dut, n_ops, shadowing=False, max_opnums=3):
for i in range(n_ops):
src1 = randint(1, dut.n_regs-1)
src2 = randint(1, dut.n_regs-1)
for i in range(n_ops):
src1 = randint(1, dut.n_regs-1)
src2 = randint(1, dut.n_regs-1)
+ imm = randint(1, (1<<dut.rwid)-1)
dest = randint(1, dut.n_regs-1)
op = randint(0, max_opnums)
dest = randint(1, dut.n_regs-1)
op = randint(0, max_opnums)
- opi = 0 if randint(0,
3
) else 1 # set true if random is nonzero
+ opi = 0 if randint(0,
2
) else 1 # set true if random is nonzero
if shadowing:
if shadowing:
- insts.append((src1, src2, dest, op, opi, (0, 0)))
+ insts.append((src1, src2, dest, op, opi,
imm,
(0, 0)))
else:
else:
- insts.append((src1, src2, dest, op, opi))
+ insts.append((src1, src2, dest, op, opi
, imm
))
return insts
return insts
@@
-955,9
+973,9
@@
def scoreboard_branch_sim(dut, alusim):
def scoreboard_sim(dut, alusim):
def scoreboard_sim(dut, alusim):
-
#seed(2
)
+
seed(0
)
- for i in range(
1
):
+ for i in range(
50
):
# set random values in the registers
for i in range(1, dut.n_regs):
# set random values in the registers
for i in range(1, dut.n_regs):
@@
-970,20
+988,27
@@
def scoreboard_sim(dut, alusim):
# create some instructions (some random, some regression tests)
instrs = []
if True:
# create some instructions (some random, some regression tests)
instrs = []
if True:
- instrs = create_random_ops(dut, 15, True, 3)
+ instrs = create_random_ops(dut, 15, True, 4)
+
+ if False:
+ instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )
if False:
instrs.append( (7, 3, 2, 4, (0, 0)) )
instrs.append( (7, 6, 6, 2, (0, 0)) )
instrs.append( (1, 7, 2, 2, (0, 0)) )
if False:
instrs.append( (7, 3, 2, 4, (0, 0)) )
instrs.append( (7, 6, 6, 2, (0, 0)) )
instrs.append( (1, 7, 2, 2, (0, 0)) )
+ if False:
+ instrs.append((2, 3, 3, 0, 0, 0, (0, 0)))
+ instrs.append((5, 3, 3, 1, 0, 0, (0, 0)))
+ instrs.append((3, 5, 5, 2, 0, 0, (0, 0)))
+ instrs.append((5, 3, 3, 3, 0, 0, (0, 0)))
+ instrs.append((3, 5, 5, 0, 0, 0, (0, 0)))
if False:
if False:
- instrs.append((2, 3, 3, 0, (0, 0)))
- instrs.append((5, 3, 3, 1, (0, 0)))
- instrs.append((3, 5, 5, 2, (0, 0)))
- instrs.append((5, 3, 3, 3, (0, 0)))
- instrs.append((3, 5, 5, 0, (0, 0)))
+ instrs.append( (3, 3, 4, 0, 0, 13979, (0, 0)))
+ instrs.append( (6, 4, 1, 2, 0, 40976, (0, 0)))
+ instrs.append( (1, 4, 7, 4, 1, 23652, (0, 0)))
if False:
instrs.append((5, 6, 2, 1))
if False:
instrs.append((5, 6, 2, 1))
@@
-1065,11
+1090,13
@@
def scoreboard_sim(dut, alusim):
# issue instruction(s), wait for issue to be free before proceeding
for i, instr in enumerate(instrs):
# issue instruction(s), wait for issue to be free before proceeding
for i, instr in enumerate(instrs):
- src1, src2, dest, op, opi, (br_ok, br_fail) = instr
+ src1, src2, dest, op, opi,
imm,
(br_ok, br_fail) = instr
- print ("instr %d: (%d, %d, %d, %d)" % (i, src1, src2, dest, op))
- alusim.op(op, opi, src1, src2, dest)
- yield from instr_q(dut, op, opi, src1, src2, dest, br_ok, br_fail)
+ print ("instr %d: (%d, %d, %d, %d, %d, %d)" % \
+ (i, src1, src2, dest, op, opi, imm))
+ alusim.op(op, opi, imm, src1, src2, dest)
+ yield from instr_q(dut, op, opi, imm, src1, src2, dest,
+ br_ok, br_fail)
# wait for all instructions to stop before checking
while True:
# wait for all instructions to stop before checking
while True: