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starting to run into things being broken in LD/ST Comp (yay)
[soc.git]
/
src
/
experiment
/
score6600.py
diff --git
a/src/experiment/score6600.py
b/src/experiment/score6600.py
index bd73e469bb792e87f3a5e604d8b2c3c9f9047d65..ccb26c1c516ad5b24391e440a954a8e0bb3c0c7b 100644
(file)
--- a/
src/experiment/score6600.py
+++ b/
src/experiment/score6600.py
@@
-202,7
+202,7
@@
class CompUnitsBase(Elaboratable):
class CompUnitLDSTs(CompUnitsBase):
class CompUnitLDSTs(CompUnitsBase):
- def __init__(self, rwid, opwid, mem):
+ def __init__(self, rwid, opwid,
n_ldsts,
mem):
""" Inputs:
* :rwid: bit width of register file(s) - both FP and INT
""" Inputs:
* :rwid: bit width of register file(s) - both FP and INT
@@
-215,11
+215,12
@@
class CompUnitLDSTs(CompUnitsBase):
self.imm_i = Signal(rwid, reset_less=True)
# Int ALUs
self.imm_i = Signal(rwid, reset_less=True)
# Int ALUs
- add1 = ALU(rwid)
- add2 = ALU(rwid)
+ alus = []
+ for i in range(n_ldsts):
+ alus.append(ALU(rwid))
units = []
units = []
- for alu in
[add1, add2]
:
+ for alu in
alus
:
aluopwid = 4 # see compldst.py for "internal" opcode
units.append(LDSTCompUnit(rwid, aluopwid, alu, mem))
aluopwid = 4 # see compldst.py for "internal" opcode
units.append(LDSTCompUnit(rwid, aluopwid, alu, mem))
@@
-401,9
+402,9
@@
class Scoreboard(Elaboratable):
self.fpregs = RegFileArray(rwid, n_regs)
# issue q needs to get at these
self.fpregs = RegFileArray(rwid, n_regs)
# issue q needs to get at these
- self.aluissue = IssueUnitGroup(4)
+ self.aluissue = IssueUnitGroup(2)
+ self.lsissue = IssueUnitGroup(2)
self.brissue = IssueUnitGroup(1)
self.brissue = IssueUnitGroup(1)
- self.lsissue = IssueUnitGroup(1)
# and these
self.alu_oper_i = Signal(4, reset_less=True)
self.alu_imm_i = Signal(rwid, reset_less=True)
# and these
self.alu_oper_i = Signal(4, reset_less=True)
self.alu_imm_i = Signal(rwid, reset_less=True)
@@
-449,15
+450,15
@@
class Scoreboard(Elaboratable):
# Int ALUs and BR ALUs
n_int_alus = 5
# Int ALUs and BR ALUs
n_int_alus = 5
- cua = CompUnitALUs(self.rwid, 3, n_alus=
4
)
+ cua = CompUnitALUs(self.rwid, 3, n_alus=
self.aluissue.n_insns
)
cub = CompUnitBR(self.rwid, 3) # 1 BR ALUs
# LDST Comp Units
n_ldsts = 2
cub = CompUnitBR(self.rwid, 3) # 1 BR ALUs
# LDST Comp Units
n_ldsts = 2
- cul = CompUnitLDSTs(self.rwid,
3
, None)
+ cul = CompUnitLDSTs(self.rwid,
4, self.lsissue.n_insns
, None)
# Comp Units
# Comp Units
- m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cu
b, cul
])
+ m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cu
l, cub
])
bgt = cub.bgt # get at the branch computation unit
br1 = cub.br1
bgt = cub.bgt # get at the branch computation unit
br1 = cub.br1
@@
-478,7
+479,7
@@
class Scoreboard(Elaboratable):
# INT/FP Issue Unit
regdecode = RegDecode(self.n_regs)
m.submodules.regdecode = regdecode
# INT/FP Issue Unit
regdecode = RegDecode(self.n_regs)
m.submodules.regdecode = regdecode
- issueunit = IssueUnitArray([self.aluissue, self.
brissue, self.ls
issue])
+ issueunit = IssueUnitArray([self.aluissue, self.
lsissue, self.br
issue])
m.submodules.issueunit = issueunit
# Shadow Matrix. currently n_intfus shadows, to be used for
m.submodules.issueunit = issueunit
# Shadow Matrix. currently n_intfus shadows, to be used for
@@
-623,9
+624,9
@@
class Scoreboard(Elaboratable):
with m.If(br1.issue_i):
sync += bspec.active_i.eq(1)
with m.If(self.branch_succ_i):
with m.If(br1.issue_i):
sync += bspec.active_i.eq(1)
with m.If(self.branch_succ_i):
- comb += bspec.good_i.eq(fn_issue_o & 0x1f)
+ comb += bspec.good_i.eq(fn_issue_o & 0x1f)
# XXX MAGIC CONSTANT
with m.If(self.branch_fail_i):
with m.If(self.branch_fail_i):
- comb += bspec.fail_i.eq(fn_issue_o & 0x1f)
+ comb += bspec.fail_i.eq(fn_issue_o & 0x1f)
# XXX MAGIC CONSTANT
# branch is active (TODO: a better signal: this is over-using the
# go_write signal - actually the branch should not be "writing")
# branch is active (TODO: a better signal: this is over-using the
# go_write signal - actually the branch should not be "writing")
@@
-765,11
+766,12
@@
class IssueToScoreboard(Elaboratable):
comb += sc.brissue.insn_i.eq(1)
comb += wait_issue_br.eq(1)
with m.Elif((op & (0x3<<4)) != 0): # ld/st
comb += sc.brissue.insn_i.eq(1)
comb += wait_issue_br.eq(1)
with m.Elif((op & (0x3<<4)) != 0): # ld/st
+ # see compldst.py
# bit 0: ADD/SUB
# bit 1: immed
# bit 4: LD
# bit 5: ST
# bit 0: ADD/SUB
# bit 1: immed
# bit 4: LD
# bit 5: ST
- comb += sc.ls_oper_i.eq(Cat(op[0], opi
, op[4:5
]))
+ comb += sc.ls_oper_i.eq(Cat(op[0], opi
[0], op[4:6
]))
comb += sc.ls_imm_i.eq(imm)
comb += sc.lsissue.insn_i.eq(1)
comb += wait_issue_ls.eq(1)
comb += sc.ls_imm_i.eq(imm)
comb += sc.lsissue.insn_i.eq(1)
comb += wait_issue_ls.eq(1)
@@
-807,6
+809,7
@@
IBLT = 5
IBEQ = 6
IBNE = 7
IBEQ = 6
IBNE = 7
+
class RegSim:
def __init__(self, rwidth, nregs):
self.rwidth = rwidth
class RegSim:
def __init__(self, rwidth, nregs):
self.rwidth = rwidth
@@
-835,6
+838,8
@@
class RegSim:
val = int(src1 == src2)
elif op == IBNE:
val = int(src1 != src2)
val = int(src1 == src2)
elif op == IBNE:
val = int(src1 != src2)
+ else:
+ return 0 # LD/ST TODO
val &= maxbits
self.setval(dest, val)
return val
val &= maxbits
self.setval(dest, val)
return val
@@
-940,6
+945,7
@@
def wait_for_busy_clear(dut):
def disable_issue(dut):
yield dut.aluissue.insn_i.eq(0)
yield dut.brissue.insn_i.eq(0)
def disable_issue(dut):
yield dut.aluissue.insn_i.eq(0)
yield dut.brissue.insn_i.eq(0)
+ yield dut.lsissue.insn_i.eq(0)
def wait_for_issue(dut, dut_issue):
def wait_for_issue(dut, dut_issue):
@@
-1084,9
+1090,12
@@
def scoreboard_sim(dut, alusim):
# create some instructions (some random, some regression tests)
instrs = []
# create some instructions (some random, some regression tests)
instrs = []
- if
Tru
e:
+ if
Fals
e:
instrs = create_random_ops(dut, 15, True, 4)
instrs = create_random_ops(dut, 15, True, 4)
+ if True: # LD test (with immediate)
+ instrs.append( (1, 2, 2, 0x10, 1, 20, (0, 0)) )
+
if False:
instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )
if False:
instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )