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big convert g/s/r mid --> muxid
[ieee754fpu.git]
/
src
/
ieee754
/
add
/
inputgroup.py
diff --git
a/src/ieee754/add/inputgroup.py
b/src/ieee754/add/inputgroup.py
index 9322c8a1598d70b521b586c7ae1eca22e6b74b62..6069817e93bcca6af8cce182a2ac9ef3a98c62e2 100644
(file)
--- a/
src/ieee754/add/inputgroup.py
+++ b/
src/ieee754/add/inputgroup.py
@@
-63,7
+63,7
@@
class InputGroup:
self.num_rows = num_rows
self.mmax = int(log(self.num_rows) / log(2))
self.rs = []
self.num_rows = num_rows
self.mmax = int(log(self.num_rows) / log(2))
self.rs = []
- self.mid = Signal(self.mmax, reset_less=True) # multiplex id
+ self.m
ux
id = Signal(self.mmax, reset_less=True) # multiplex id
for i in range(num_rows):
self.rs.append(FPGetSyncOpsMod(width, num_ops))
self.rs = Array(self.rs)
for i in range(num_rows):
self.rs.append(FPGetSyncOpsMod(width, num_ops))
self.rs = Array(self.rs)
@@
-92,7
+92,7
@@
class InputGroup:
# encoder active: ack relevant input, record MID, pass output
with m.If(out_en):
rs = self.rs[pe.o]
# encoder active: ack relevant input, record MID, pass output
with m.If(out_en):
rs = self.rs[pe.o]
- m.d.sync += self.mid.eq(pe.o)
+ m.d.sync += self.m
ux
id.eq(pe.o)
m.d.sync += rs.ack.eq(0)
m.d.sync += self.out_op.stb.eq(0)
for j in range(self.num_ops):
m.d.sync += rs.ack.eq(0)
m.d.sync += self.out_op.stb.eq(0)
for j in range(self.num_ops):
@@
-110,6
+110,6
@@
class InputGroup:
for i in range(self.num_rows):
inop = self.rs[i]
res += inop.in_op + [inop.stb]
for i in range(self.num_rows):
inop = self.rs[i]
res += inop.in_op + [inop.stb]
- return self.out_op.ports() + res + [self.mid]
+ return self.out_op.ports() + res + [self.m
ux
id]