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big convert g/s/r mid --> muxid
[ieee754fpu.git]
/
src
/
ieee754
/
fpadd
/
statemachine.py
diff --git
a/src/ieee754/fpadd/statemachine.py
b/src/ieee754/fpadd/statemachine.py
index 0ca7ce7a490f761214ea13846e555b80d9e80205..decbc3d4e87f58630df8afe797d03398a186e857 100644
(file)
--- a/
src/ieee754/fpadd/statemachine.py
+++ b/
src/ieee754/fpadd/statemachine.py
@@
-33,14
+33,14
@@
class FPOpData:
def __init__(self, width, id_wid):
self.z = FPOpOut(width)
self.z.data_o = Signal(width)
def __init__(self, width, id_wid):
self.z = FPOpOut(width)
self.z.data_o = Signal(width)
- self.mid = Signal(id_wid, reset_less=True)
+ self.m
ux
id = Signal(id_wid, reset_less=True)
def __iter__(self):
yield self.z
def __iter__(self):
yield self.z
- yield self.mid
+ yield self.m
ux
id
def eq(self, i):
def eq(self, i):
- return [self.z.eq(i.z), self.mid.eq(i.mid)]
+ return [self.z.eq(i.z), self.m
ux
id.eq(i.mid)]
def ports(self):
return list(self)
def ports(self):
return list(self)