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big convert g/s/r mid --> muxid
[ieee754fpu.git]
/
src
/
ieee754
/
fpcommon
/
getop.py
diff --git
a/src/ieee754/fpcommon/getop.py
b/src/ieee754/fpcommon/getop.py
index 17a8334bd13ba1998822a7d0c32f7f58849f01fe..5ca46bfdc281464d0d1a8e220b8c68694d6b166e 100644
(file)
--- a/
src/ieee754/fpcommon/getop.py
+++ b/
src/ieee754/fpcommon/getop.py
@@
-73,13
+73,13
@@
class FPNumBase2Ops:
def __init__(self, width, id_wid, m_extra=True):
self.a = FPNumBase(width, m_extra)
self.b = FPNumBase(width, m_extra)
def __init__(self, width, id_wid, m_extra=True):
self.a = FPNumBase(width, m_extra)
self.b = FPNumBase(width, m_extra)
- self.mid = Signal(id_wid, reset_less=True)
+ self.m
ux
id = Signal(id_wid, reset_less=True)
def eq(self, i):
def eq(self, i):
- return [self.a.eq(i.a), self.b.eq(i.b), self.m
id.eq(i.m
id)]
+ return [self.a.eq(i.a), self.b.eq(i.b), self.m
uxid.eq(i.mux
id)]
def ports(self):
def ports(self):
- return [self.a, self.b, self.mid]
+ return [self.a, self.b, self.m
ux
id]
class FPBaseData:
class FPBaseData:
@@
-89,17
+89,17
@@
class FPBaseData:
print (pspec)
self.id_wid = pspec['id_wid']
self.op_wid = pspec.get('op_wid', 0)
print (pspec)
self.id_wid = pspec['id_wid']
self.op_wid = pspec.get('op_wid', 0)
- self.mid = Signal(self.id_wid, reset_less=True) # RS multiplex ID
+ self.m
ux
id = Signal(self.id_wid, reset_less=True) # RS multiplex ID
self.op = Signal(self.op_wid, reset_less=True)
def eq(self, i):
self.op = Signal(self.op_wid, reset_less=True)
def eq(self, i):
- ret = [self.m
id.eq(i.m
id)]
+ ret = [self.m
uxid.eq(i.mux
id)]
if self.op_wid:
ret.append(self.op.eq(i.op))
return ret
def __iter__(self):
if self.op_wid:
ret.append(self.op.eq(i.op))
return ret
def __iter__(self):
- yield self.mid
+ yield self.m
ux
id
if self.op_wid:
yield self.op
if self.op_wid:
yield self.op
@@
-118,7
+118,7
@@
class FPADDBaseData:
operand = Signal(width, name=name)
setattr(self, name, operand)
ops.append(operand)
operand = Signal(width, name=name)
setattr(self, name, operand)
ops.append(operand)
- self.m
id = self.ctx.m
id # make muxid available here: complicated
+ self.m
uxid = self.ctx.mux
id # make muxid available here: complicated
self.ops = ops
def eq(self, i):
self.ops = ops
def eq(self, i):