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big convert g/s/r mid --> muxid
[ieee754fpu.git]
/
src
/
ieee754
/
fpdiv
/
div0.py
diff --git
a/src/ieee754/fpdiv/div0.py
b/src/ieee754/fpdiv/div0.py
index 796e6c29c09bd835dae1f396daa2cd597900fe88..2ad8bcdae5435c285834ac91a7e2690681c84b37 100644
(file)
--- a/
src/ieee754/fpdiv/div0.py
+++ b/
src/ieee754/fpdiv/div0.py
@@
-6,17
+6,22
@@
Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
from nmigen import Module, Signal, Cat, Elaboratable
from nmigen.cli import main, verilog
from nmigen import Module, Signal, Cat, Elaboratable
from nmigen.cli import main, verilog
-from ieee754.fpcommon.fpbase import
FPNumBaseRecord
+from ieee754.fpcommon.fpbase import
(FPNumBaseRecord, Overflow)
from ieee754.fpcommon.fpbase import FPState
from ieee754.fpcommon.denorm import FPSCData
from ieee754.fpcommon.fpbase import FPState
from ieee754.fpcommon.denorm import FPSCData
+from ieee754.fpcommon.getop import FPBaseData
class FPDivStage0Data:
class FPDivStage0Data:
- def __init__(self, width,
id_wid
):
+ def __init__(self, width,
pspec
):
self.z = FPNumBaseRecord(width, False)
self.out_do_z = Signal(reset_less=True)
self.oz = Signal(width, reset_less=True)
self.z = FPNumBaseRecord(width, False)
self.out_do_z = Signal(reset_less=True)
self.oz = Signal(width, reset_less=True)
+ self.of = Overflow()
+
+ self.ctx = FPBaseData(width, pspec) # context: muxid, operator etc.
+ self.muxid = self.ctx.muxid # annoying. complicated.
# TODO: here is where Q and R would be put, and passed
# down to Stage1 processing.
# TODO: here is where Q and R would be put, and passed
# down to Stage1 processing.
@@
-24,11
+29,10
@@
class FPDivStage0Data:
mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
self.product = Signal(mw, reset_less=True)
mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
self.product = Signal(mw, reset_less=True)
- self.mid = Signal(id_wid, reset_less=True)
-
def eq(self, i):
return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
def eq(self, i):
return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
- self.product.eq(i.product), self.mid.eq(i.mid)]
+ self.of.eq(i.of),
+ self.product.eq(i.product), self.ctx.eq(i.ctx)]
class FPDivStage0Mod(Elaboratable):
class FPDivStage0Mod(Elaboratable):
@@
-58,9
+62,13
@@
class FPDivStage0Mod(Elaboratable):
m = Module()
# XXX TODO, actual DIV code here. this class would be
m = Module()
# XXX TODO, actual DIV code here. this class would be
- # "step one" which takes the pre-normalised data and
+ # "step one" which takes the pre-normalised data
(see ispec)
and
# *begins* the processing phase (enters the massive DIV
# *begins* the processing phase (enters the massive DIV
- # pipeline chain)
+ # pipeline chain) - see ospec.
+
+ # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
+ # it is PURELY the *ENTRY* point into the chain, performing
+ # "preparation" work
# store intermediate tests (and zero-extended mantissas)
am0 = Signal(len(self.i.a.m)+1, reset_less=True)
# store intermediate tests (and zero-extended mantissas)
am0 = Signal(len(self.i.a.m)+1, reset_less=True)
@@
-80,7
+88,7
@@
class FPDivStage0Mod(Elaboratable):
m.d.comb += self.o.oz.eq(self.i.oz)
m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
m.d.comb += self.o.oz.eq(self.i.oz)
m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
- m.d.comb += self.o.
mid.eq(self.i.mid
)
+ m.d.comb += self.o.
ctx.eq(self.i.ctx
)
return m
return m