+class IntermediateOut(Elaboratable):
+ """ selects the HI/LO part of the multiplication, for a given bit-width
+ the output is also reconstructed in its SIMD (partition) lanes.
+ """
+ def __init__(self, width, out_wid, n_parts):
+ self.width = width
+ self.n_parts = n_parts
+ self.part_ops = [Signal(2, name="dpop%d" % i, reset_less=True)
+ for i in range(8)]
+ self.intermed = Signal(out_wid, reset_less=True)
+ self.output = Signal(out_wid//2, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ ol = []
+ w = self.width
+ sel = w // 8
+ for i in range(self.n_parts):
+ op = Signal(w, reset_less=True, name="op%d_%d" % (w, i))
+ m.d.comb += op.eq(
+ Mux(self.part_ops[sel * i] == OP_MUL_LOW,
+ self.intermed.part(i * w*2, w),
+ self.intermed.part(i * w*2 + w, w)))
+ ol.append(op)
+ m.d.comb += self.output.eq(Cat(*ol))
+
+ return m
+
+
+class FinalOut(Elaboratable):
+ """ selects the final output based on the partitioning.
+
+ each byte is selectable independently, i.e. it is possible
+ that some partitions requested 8-bit computation whilst others
+ requested 16 or 32 bit.
+ """
+ def __init__(self, output_width, n_parts, part_pts):
+ self.part_pts = part_pts
+ self.i = IntermediateData(part_pts, output_width, n_parts)
+ self.out_wid = output_width//2
+ # output
+ self.out = Signal(self.out_wid, reset_less=True)
+ self.intermediate_output = Signal(output_width, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ part_pts = self.part_pts
+ m.submodules.p_8 = p_8 = Parts(8, part_pts, 8)
+ m.submodules.p_16 = p_16 = Parts(8, part_pts, 4)
+ m.submodules.p_32 = p_32 = Parts(8, part_pts, 2)
+ m.submodules.p_64 = p_64 = Parts(8, part_pts, 1)
+
+ out_part_pts = self.i.part_pts
+
+ # temporaries
+ d8 = [Signal(name=f"d8_{i}", reset_less=True) for i in range(8)]
+ d16 = [Signal(name=f"d16_{i}", reset_less=True) for i in range(4)]
+ d32 = [Signal(name=f"d32_{i}", reset_less=True) for i in range(2)]
+
+ i8 = Signal(self.out_wid, reset_less=True)
+ i16 = Signal(self.out_wid, reset_less=True)
+ i32 = Signal(self.out_wid, reset_less=True)
+ i64 = Signal(self.out_wid, reset_less=True)
+
+ m.d.comb += p_8.part_pts.eq(out_part_pts)
+ m.d.comb += p_16.part_pts.eq(out_part_pts)
+ m.d.comb += p_32.part_pts.eq(out_part_pts)
+ m.d.comb += p_64.part_pts.eq(out_part_pts)
+
+ for i in range(len(p_8.parts)):
+ m.d.comb += d8[i].eq(p_8.parts[i])
+ for i in range(len(p_16.parts)):
+ m.d.comb += d16[i].eq(p_16.parts[i])
+ for i in range(len(p_32.parts)):
+ m.d.comb += d32[i].eq(p_32.parts[i])
+ m.d.comb += i8.eq(self.i.outputs[0])
+ m.d.comb += i16.eq(self.i.outputs[1])
+ m.d.comb += i32.eq(self.i.outputs[2])
+ m.d.comb += i64.eq(self.i.outputs[3])
+
+ ol = []
+ for i in range(8):
+ # select one of the outputs: d8 selects i8, d16 selects i16
+ # d32 selects i32, and the default is i64.
+ # d8 and d16 are ORed together in the first Mux
+ # then the 2nd selects either i8 or i16.
+ # if neither d8 nor d16 are set, d32 selects either i32 or i64.
+ op = Signal(8, reset_less=True, name="op_%d" % i)
+ m.d.comb += op.eq(
+ Mux(d8[i] | d16[i // 2],
+ Mux(d8[i], i8.part(i * 8, 8), i16.part(i * 8, 8)),
+ Mux(d32[i // 4], i32.part(i * 8, 8), i64.part(i * 8, 8))))
+ ol.append(op)
+ m.d.comb += self.out.eq(Cat(*ol))
+ m.d.comb += self.intermediate_output.eq(self.i.intermediate_output)
+ return m
+
+
+class OrMod(Elaboratable):
+ """ ORs four values together in a hierarchical tree
+ """
+ def __init__(self, wid):
+ self.wid = wid
+ self.orin = [Signal(wid, name="orin%d" % i, reset_less=True)
+ for i in range(4)]
+ self.orout = Signal(wid, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ or1 = Signal(self.wid, reset_less=True)
+ or2 = Signal(self.wid, reset_less=True)
+ m.d.comb += or1.eq(self.orin[0] | self.orin[1])
+ m.d.comb += or2.eq(self.orin[2] | self.orin[3])
+ m.d.comb += self.orout.eq(or1 | or2)
+
+ return m
+
+
+class Signs(Elaboratable):
+ """ determines whether a or b are signed numbers
+ based on the required operation type (OP_MUL_*)
+ """
+
+ def __init__(self):
+ self.part_ops = Signal(2, reset_less=True)
+ self.a_signed = Signal(reset_less=True)
+ self.b_signed = Signal(reset_less=True)
+
+ def elaborate(self, platform):
+
+ m = Module()
+
+ asig = self.part_ops != OP_MUL_UNSIGNED_HIGH
+ bsig = (self.part_ops == OP_MUL_LOW) \
+ | (self.part_ops == OP_MUL_SIGNED_HIGH)
+ m.d.comb += self.a_signed.eq(asig)
+ m.d.comb += self.b_signed.eq(bsig)
+
+ return m
+
+
+class IntermediateData:
+
+ def __init__(self, part_pts, output_width, n_parts):
+ self.part_ops = [Signal(2, name=f"part_ops_{i}", reset_less=True)
+ for i in range(n_parts)]
+ self.part_pts = part_pts.like()
+ self.outputs = [Signal(output_width, name="io%d" % i, reset_less=True)
+ for i in range(4)]
+ # intermediates (needed for unit tests)
+ self.intermediate_output = Signal(output_width)
+
+ def eq_from(self, part_pts, outputs, intermediate_output,
+ part_ops):
+ return [self.part_pts.eq(part_pts)] + \
+ [self.intermediate_output.eq(intermediate_output)] + \
+ [self.outputs[i].eq(outputs[i])
+ for i in range(4)] + \
+ [self.part_ops[i].eq(part_ops[i])
+ for i in range(len(self.part_ops))]
+
+ def eq(self, rhs):
+ return self.eq_from(rhs.part_pts, rhs.outputs,
+ rhs.intermediate_output, rhs.part_ops)
+
+
+class AllTermsData:
+
+ def __init__(self, partition_points):
+ self.a = Signal(64)
+ self.b = Signal(64)
+ self.part_pts = partition_points.like()
+ self.part_ops = [Signal(2, name=f"part_ops_{i}") for i in range(8)]
+
+ def eq_from(self, part_pts, inputs, part_ops):
+ return [self.part_pts.eq(part_pts)] + \
+ [self.a.eq(a), self.b.eq(b)] + \
+ [self.part_ops[i].eq(part_ops[i])
+ for i in range(len(self.part_ops))]
+
+ def eq(self, rhs):
+ return self.eq_from(rhs.part_pts, rhs.a, rhs.b, rhs.part_ops)
+
+
+class AllTerms(Elaboratable):
+ """Set of terms to be added together
+ """
+
+ def __init__(self, n_inputs, output_width, n_parts, register_levels,
+ partition_points):
+ """Create an ``AddReduce``.
+
+ :param inputs: input ``Signal``s to be summed.
+ :param output_width: bit-width of ``output``.
+ :param register_levels: List of nesting levels that should have
+ pipeline registers.
+ :param partition_points: the input partition points.
+ """
+ self.i = AllTermsData(partition_points)
+ self.register_levels = register_levels
+ self.n_inputs = n_inputs
+ self.n_parts = n_parts
+ self.output_width = output_width
+ self.o = AddReduceData(self.i.part_pts, n_inputs,
+ output_width, n_parts)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ eps = self.i.part_pts
+
+ # collect part-bytes
+ pbs = Signal(8, reset_less=True)
+ tl = []
+ for i in range(8):
+ pb = Signal(name="pb%d" % i, reset_less=True)
+ m.d.comb += pb.eq(eps.part_byte(i))
+ tl.append(pb)
+ m.d.comb += pbs.eq(Cat(*tl))
+
+ # local variables
+ signs = []
+ for i in range(8):
+ s = Signs()
+ signs.append(s)
+ setattr(m.submodules, "signs%d" % i, s)
+ m.d.comb += s.part_ops.eq(self.i.part_ops[i])
+
+ n_levels = len(self.register_levels)+1
+ m.submodules.part_8 = part_8 = Part(eps, 128, 8, n_levels, 8)
+ m.submodules.part_16 = part_16 = Part(eps, 128, 4, n_levels, 8)
+ m.submodules.part_32 = part_32 = Part(eps, 128, 2, n_levels, 8)
+ m.submodules.part_64 = part_64 = Part(eps, 128, 1, n_levels, 8)
+ nat_l, nbt_l, nla_l, nlb_l = [], [], [], []
+ for mod in [part_8, part_16, part_32, part_64]:
+ m.d.comb += mod.a.eq(self.i.a)
+ m.d.comb += mod.b.eq(self.i.b)
+ for i in range(len(signs)):
+ m.d.comb += mod.a_signed[i].eq(signs[i].a_signed)
+ m.d.comb += mod.b_signed[i].eq(signs[i].b_signed)
+ m.d.comb += mod.pbs.eq(pbs)
+ nat_l.append(mod.not_a_term)
+ nbt_l.append(mod.not_b_term)
+ nla_l.append(mod.neg_lsb_a_term)
+ nlb_l.append(mod.neg_lsb_b_term)
+
+ terms = []
+
+ for a_index in range(8):
+ t = ProductTerms(8, 128, 8, a_index, 8)
+ setattr(m.submodules, "terms_%d" % a_index, t)
+
+ m.d.comb += t.a.eq(self.i.a)
+ m.d.comb += t.b.eq(self.i.b)
+ m.d.comb += t.pb_en.eq(pbs)
+
+ for term in t.terms:
+ terms.append(term)
+
+ # it's fine to bitwise-or data together since they are never enabled
+ # at the same time
+ m.submodules.nat_or = nat_or = OrMod(128)
+ m.submodules.nbt_or = nbt_or = OrMod(128)
+ m.submodules.nla_or = nla_or = OrMod(128)
+ m.submodules.nlb_or = nlb_or = OrMod(128)
+ for l, mod in [(nat_l, nat_or),
+ (nbt_l, nbt_or),
+ (nla_l, nla_or),
+ (nlb_l, nlb_or)]:
+ for i in range(len(l)):
+ m.d.comb += mod.orin[i].eq(l[i])
+ terms.append(mod.orout)
+
+ # copy the intermediate terms to the output
+ for i, value in enumerate(terms):
+ m.d.comb += self.o.terms[i].eq(value)
+
+ # copy reg part points and part ops to output
+ m.d.comb += self.o.part_pts.eq(eps)
+ m.d.comb += [self.o.part_ops[i].eq(self.i.part_ops[i])
+ for i in range(len(self.i.part_ops))]
+
+ return m
+
+
+class Intermediates(Elaboratable):
+ """ Intermediate output modules
+ """
+
+ def __init__(self, output_width, n_parts, partition_points):
+ self.i = FinalReduceData(partition_points, output_width, n_parts)
+ self.o = IntermediateData(partition_points, output_width, n_parts)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ out_part_ops = self.i.part_ops
+ out_part_pts = self.i.part_pts
+
+ # create _output_64
+ m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
+ m.d.comb += io64.intermed.eq(self.i.output)
+ for i in range(8):
+ m.d.comb += io64.part_ops[i].eq(out_part_ops[i])
+ m.d.comb += self.o.outputs[3].eq(io64.output)
+
+ # create _output_32
+ m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
+ m.d.comb += io32.intermed.eq(self.i.output)
+ for i in range(8):
+ m.d.comb += io32.part_ops[i].eq(out_part_ops[i])
+ m.d.comb += self.o.outputs[2].eq(io32.output)
+
+ # create _output_16
+ m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
+ m.d.comb += io16.intermed.eq(self.i.output)
+ for i in range(8):
+ m.d.comb += io16.part_ops[i].eq(out_part_ops[i])
+ m.d.comb += self.o.outputs[1].eq(io16.output)
+
+ # create _output_8
+ m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
+ m.d.comb += io8.intermed.eq(self.i.output)
+ for i in range(8):
+ m.d.comb += io8.part_ops[i].eq(out_part_ops[i])
+ m.d.comb += self.o.outputs[0].eq(io8.output)
+
+ for i in range(8):
+ m.d.comb += self.o.part_ops[i].eq(out_part_ops[i])
+ m.d.comb += self.o.part_pts.eq(out_part_pts)
+ m.d.comb += self.o.intermediate_output.eq(self.i.output)
+
+ return m
+
+