+ assert self.n_inputs % FULL_ADDER_INPUT_COUNT == 0
+
+ self._intermediate_terms = _intermediate_terms
+
+
+class AddReduce(Elaboratable):
+ """Recursively Add list of numbers together.
+
+ :attribute inputs: input ``Signal``s to be summed. Modification not
+ supported, except for by ``Signal.eq``.
+ :attribute register_levels: List of nesting levels that should have
+ pipeline registers.
+ :attribute output: output sum.
+ :attribute partition_points: the input partition points. Modification not
+ supported, except for by ``Signal.eq``.
+ """
+
+ def __init__(self, inputs, output_width, register_levels, partition_points,
+ part_ops):
+ """Create an ``AddReduce``.
+
+ :param inputs: input ``Signal``s to be summed.
+ :param output_width: bit-width of ``output``.
+ :param register_levels: List of nesting levels that should have
+ pipeline registers.
+ :param partition_points: the input partition points.
+ """
+ self.inputs = inputs
+ self.part_ops = part_ops
+ n_parts = len(part_ops)
+ self.o = FinalReduceData(partition_points, output_width, n_parts)
+ self.output_width = output_width
+ self.register_levels = register_levels
+ self.partition_points = partition_points
+
+ self.create_levels()
+
+ @staticmethod
+ def get_max_level(input_count):
+ return AddReduceSingle.get_max_level(input_count)
+
+ @staticmethod
+ def next_register_levels(register_levels):
+ """``Iterable`` of ``register_levels`` for next recursive level."""
+ for level in register_levels:
+ if level > 0:
+ yield level - 1
+
+ def create_levels(self):
+ """creates reduction levels"""
+
+ mods = []
+ next_levels = self.register_levels
+ partition_points = self.partition_points
+ part_ops = self.part_ops
+ n_parts = len(part_ops)
+ inputs = self.inputs
+ ilen = len(inputs)
+ while True:
+ next_level = AddReduceSingle(ilen, self.output_width, n_parts,
+ next_levels, partition_points)
+ mods.append(next_level)
+ next_levels = list(AddReduce.next_register_levels(next_levels))
+ partition_points = next_level.i.reg_partition_points
+ inputs = next_level.o.inputs
+ ilen = len(inputs)
+ part_ops = next_level.i.part_ops
+ groups = AddReduceSingle.full_adder_groups(len(inputs))
+ if len(groups) == 0:
+ break
+
+ next_level = FinalAdd(ilen, self.output_width, n_parts,
+ next_levels, partition_points)
+ mods.append(next_level)
+
+ self.levels = mods
+
+ def elaborate(self, platform):
+ """Elaborate this module."""
+ m = Module()
+
+ for i, next_level in enumerate(self.levels):
+ setattr(m.submodules, "next_level%d" % i, next_level)
+
+ partition_points = self.partition_points
+ inputs = self.inputs
+ part_ops = self.part_ops
+ n_parts = len(part_ops)
+ n_inputs = len(inputs)
+ output_width = self.output_width
+ i = AddReduceData(partition_points, n_inputs, output_width, n_parts)
+ m.d.comb += i.eq_from(partition_points, inputs, part_ops)
+ for idx in range(len(self.levels)):
+ mcur = self.levels[idx]
+ if 0 in mcur.register_levels:
+ m.d.sync += mcur.i.eq(i)
+ else:
+ m.d.comb += mcur.i.eq(i)
+ i = mcur.o # for next loop
+
+ # output comes from last module
+ m.d.comb += self.o.eq(i)
+