projects
/
ieee754fpu.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
skip add clock on combinatorial tests
[ieee754fpu.git]
/
src
/
ieee754
/
part_mul_add
/
test
/
test_multiply.py
diff --git
a/src/ieee754/part_mul_add/test/test_multiply.py
b/src/ieee754/part_mul_add/test/test_multiply.py
index 0c0b420b7f53cbeb9623207fba82eabaf8221bc1..3287cbe4c6c1c304545b36f8790533b677412c78 100644
(file)
--- a/
src/ieee754/part_mul_add/test/test_multiply.py
+++ b/
src/ieee754/part_mul_add/test/test_multiply.py
@@
-14,11
+14,19
@@
import unittest
from hashlib import sha256
import enum
import pdb
from hashlib import sha256
import enum
import pdb
+from nmigen.cli import verilog, rtlil
+
+
+def create_ilang(dut, traces, test_name):
+ vl = rtlil.convert(dut, ports=traces)
+ with open("%s.il" % test_name, "w") as f:
+ f.write(vl)
def create_simulator(module: Any,
traces: List[Signal],
test_name: str) -> Simulator:
def create_simulator(module: Any,
traces: List[Signal],
test_name: str) -> Simulator:
+ create_ilang(module, traces, test_name)
return Simulator(module,
vcd_file=open(test_name + ".vcd", "w"),
gtkw_file=open(test_name + ".gtkw", "w"),
return Simulator(module,
vcd_file=open(test_name + ".vcd", "w"),
gtkw_file=open(test_name + ".gtkw", "w"),
@@
-48,10
+56,10
@@
class TestPartitionPoints(unittest.TestCase):
self.assertEqual((yield partition_points[1]), True)
self.assertEqual((yield partition_points[5]), False)
yield partition_point_10.eq(0)
self.assertEqual((yield partition_points[1]), True)
self.assertEqual((yield partition_points[5]), False)
yield partition_point_10.eq(0)
- yield Delay(1e-6)
+ yield Delay(
0.
1e-6)
self.assertEqual((yield mask), 0xFFFD)
yield partition_point_10.eq(1)
self.assertEqual((yield mask), 0xFFFD)
yield partition_point_10.eq(1)
- yield Delay(1e-6)
+ yield Delay(
0.
1e-6)
self.assertEqual((yield mask), 0xFBFD)
sim.add_process(async_process)
self.assertEqual((yield mask), 0xFBFD)
sim.add_process(async_process)
@@
-86,7
+94,7
@@
class TestPartitionedAdder(unittest.TestCase):
(0x0000, 0xFFFF)]:
yield module.a.eq(a)
yield module.b.eq(b)
(0x0000, 0xFFFF)]:
yield module.a.eq(a)
yield module.b.eq(b)
- yield Delay(1e-6)
+ yield Delay(
0.
1e-6)
y = 0
for mask in mask_list:
y |= mask & ((a & mask) + (b & mask))
y = 0
for mask in mask_list:
y |= mask & ((a & mask) + (b & mask))
@@
-146,14
+154,14
@@
class TestAddReduce(unittest.TestCase):
if gen_or_check == GenOrCheck.Generate:
for i, v in zip(inputs, values):
yield i.eq(v)
if gen_or_check == GenOrCheck.Generate:
for i, v in zip(inputs, values):
yield i.eq(v)
- yield Delay(1e-6)
+ yield Delay(
0.
1e-6)
y = 0
for mask in mask_list:
v = 0
for value in values:
v += value & mask
y |= mask & v
y = 0
for mask in mask_list:
v = 0
for value in values:
v += value & mask
y |= mask & v
- output = (yield module.output)
+ output = (yield module.o
.o
utput)
if gen_or_check == GenOrCheck.Check:
self.assertEqual(y, output, f"0x{y:X} != 0x{output:X}")
yield Tick()
if gen_or_check == GenOrCheck.Check:
self.assertEqual(y, output, f"0x{y:X} != 0x{output:X}")
yield Tick()
@@
-227,7
+235,8
@@
class TestAddReduce(unittest.TestCase):
yield Tick()
yield from generic_process(GenOrCheck.Check)
yield Tick()
yield from generic_process(GenOrCheck.Check)
- sim.add_clock(2e-6)
+ if "sync" in sim._domains:
+ sim.add_clock(2e-6)
sim.add_process(generate_process)
sim.add_process(check_process)
sim.run()
sim.add_process(generate_process)
sim.add_process(check_process)
sim.run()
@@
-250,17
+259,15
@@
class TestAddReduce(unittest.TestCase):
module = AddReduce(inputs,
width,
register_levels,
module = AddReduce(inputs,
width,
register_levels,
- partition_points)
+ partition_points,
+ [])
file_name = "add_reduce"
if len(register_levels) != 0:
file_name += f"-{'_'.join(map(repr, register_levels))}"
file_name += f"-{input_count:02d}"
file_name = "add_reduce"
if len(register_levels) != 0:
file_name += f"-{'_'.join(map(repr, register_levels))}"
file_name += f"-{input_count:02d}"
- with create_simulator(module,
- [partition_4,
- partition_8,
- *inputs,
- module.output],
- file_name) as sim:
+ ports = [partition_4, partition_8, *inputs, module.o.output]
+ #create_ilang(module, ports, file_name)
+ with create_simulator(module, ports, file_name) as sim:
self.subtest_run_sim(input_count,
sim,
partition_4,
self.subtest_run_sim(input_count,
sim,
partition_4,
@@
-453,9
+460,9
@@
class TestMul8_16_32_64(unittest.TestCase):
yield module.a.eq(a)
yield module.b.eq(b)
output2, intermediate_output2 = self.simd_mul(a, b, lanes)
yield module.a.eq(a)
yield module.b.eq(b)
output2, intermediate_output2 = self.simd_mul(a, b, lanes)
- yield Delay(1e-6)
+ yield Delay(
0.
1e-6)
if gen_or_check == GenOrCheck.Check:
if gen_or_check == GenOrCheck.Check:
- intermediate_output = (yield module.
_
intermediate_output)
+ intermediate_output = (yield module.intermediate_output)
self.assertEqual(intermediate_output,
intermediate_output2,
f"0x{intermediate_output:X} "
self.assertEqual(intermediate_output,
intermediate_output2,
f"0x{intermediate_output:X} "
@@
-521,16
+528,10
@@
class TestMul8_16_32_64(unittest.TestCase):
file_name += f"-{'_'.join(map(repr, register_levels))}"
ports = [module.a,
module.b,
file_name += f"-{'_'.join(map(repr, register_levels))}"
ports = [module.a,
module.b,
- module.
_
intermediate_output,
+ module.intermediate_output,
module.output]
ports.extend(module.part_ops)
ports.extend(module.part_pts.values())
module.output]
ports.extend(module.part_ops)
ports.extend(module.part_pts.values())
- ports += [module._output_64,
- module._output_32,
- module._output_16,
- module._output_8]
- ports.extend(module._a_signed)
- ports.extend(module._b_signed)
with create_simulator(module, ports, file_name) as sim:
def process(gen_or_check: GenOrCheck) -> AsyncProcessGenerator:
for a_signed in False, True:
with create_simulator(module, ports, file_name) as sim:
def process(gen_or_check: GenOrCheck) -> AsyncProcessGenerator:
for a_signed in False, True:
@@
-632,7
+633,8
@@
class TestMul8_16_32_64(unittest.TestCase):
yield Tick()
yield from process(GenOrCheck.Check)
yield Tick()
yield from process(GenOrCheck.Check)
- sim.add_clock(2e-6)
+ if "sync" in sim._domains:
+ sim.add_clock(2e-6)
sim.add_process(generate_process)
sim.add_process(check_process)
sim.run()
sim.add_process(generate_process)
sim.add_process(check_process)
sim.run()