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SDRAM uses SDR0MemBase now
[shakti-core.git]
/
src
/
lib
/
MemoryMap.bsv
diff --git
a/src/lib/MemoryMap.bsv
b/src/lib/MemoryMap.bsv
index 4f811319fc10a82644bb1f097ffd2682da91bc12..9281366440bcc2d40cb3997be85864561fe8bc5a 100644
(file)
--- a/
src/lib/MemoryMap.bsv
+++ b/
src/lib/MemoryMap.bsv
@@
-33,6
+33,8
@@
package MemoryMap;
import defined_types::*;
import fast_memory_map::*;
import slow_memory_map::*;
import defined_types::*;
import fast_memory_map::*;
import slow_memory_map::*;
+ `include "slow_instance_defines.bsv"
+ `include "fast_instance_defines.bsv"
`include "instance_defines.bsv"
`include "core_parameters.bsv"
/*========================= */
`include "instance_defines.bsv"
`include "core_parameters.bsv"
/*========================= */
@@
-60,15
+62,13
@@
endfunction
function Bool is_IO_Addr(Bit#(`PADDR) addr); // TODO Shuold be PADDR
if(addr>=`DebugBase && addr<=`DebugEnd)
return (True);
function Bool is_IO_Addr(Bit#(`PADDR) addr); // TODO Shuold be PADDR
if(addr>=`DebugBase && addr<=`DebugEnd)
return (True);
- else
- `ifdef SDR0_0_Base
- if(addr>=`SDR0_0_Base && addr<=`SDR0_0_End)
+ `ifdef SDR0MemBase
+ else if(addr>=`SDR0MemBase && addr<=`SDR0MemEnd)
`ifdef FlexBus
`ifdef FlexBus
-
return (True);
+ return (True);
`else
return (False);
`else
return (False);
- `else
- return (False);
+ `endif
`endif
`ifdef BOOTROM
else if(addr>=`BootRomBase && addr<=`BootRomEnd)
`endif
`ifdef BOOTROM
else if(addr>=`BootRomBase && addr<=`BootRomEnd)