projects
/
shakti-core.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
SDRAM uses SDR0MemBase now
[shakti-core.git]
/
src
/
lib
/
MemoryMap.bsv
diff --git
a/src/lib/MemoryMap.bsv
b/src/lib/MemoryMap.bsv
index a4fbfda4e724bfea62982bf161134da5e515b8a4..9281366440bcc2d40cb3997be85864561fe8bc5a 100644
(file)
--- a/
src/lib/MemoryMap.bsv
+++ b/
src/lib/MemoryMap.bsv
@@
-31,21
+31,23
@@
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
package MemoryMap;
/*=== Project imports ==== */
import defined_types::*;
package MemoryMap;
/*=== Project imports ==== */
import defined_types::*;
- import soc::*;
- import slow_peripherals::*;
+ import fast_memory_map::*;
+ import slow_memory_map::*;
+ `include "slow_instance_defines.bsv"
+ `include "fast_instance_defines.bsv"
`include "instance_defines.bsv"
`include "core_parameters.bsv"
/*========================= */
`include "instance_defines.bsv"
`include "core_parameters.bsv"
/*========================= */
-function Tuple2 #(Bool, Bit#(TLog#(Num_Slaves)))
+function Tuple2 #(Bool, Bit#(TLog#(Num_
Fast_
Slaves)))
fn_addr_to_slave_num (Bit#(`PADDR) addr);
fn_addr_to_slave_num (Bit#(`PADDR) addr);
- let ft =
FastTuple2
;
+ let ft =
fn_addr_to_fastslave_num(addr)
;
Bool isfast = tpl_1(ft);
Bool isfast = tpl_1(ft);
- Bit#(TLog#(Num_Slaves)) x = tpl_2(ft);
+ Bit#(TLog#(Num_
Fast_
Slaves)) x = tpl_2(ft);
- let st =
SlowTuple2
;
+ let st =
fn_slow_address_mapping(addr)
;
Bool isslow = tpl_1(st);
Bit#(TLog#(Num_Slow_Slaves)) y = tpl_2(st);
if (isfast)
Bool isslow = tpl_1(st);
Bit#(TLog#(Num_Slow_Slaves)) y = tpl_2(st);
if (isfast)
@@
-60,11
+62,13
@@
endfunction
function Bool is_IO_Addr(Bit#(`PADDR) addr); // TODO Shuold be PADDR
if(addr>=`DebugBase && addr<=`DebugEnd)
return (True);
function Bool is_IO_Addr(Bit#(`PADDR) addr); // TODO Shuold be PADDR
if(addr>=`DebugBase && addr<=`DebugEnd)
return (True);
- else if(addr>=`SDRAMMemBase && addr<=`SDRAMMemEnd)
- `ifdef FlexBus
+ `ifdef SDR0MemBase
+ else if(addr>=`SDR0MemBase && addr<=`SDR0MemEnd)
+ `ifdef FlexBus
return (True);
return (True);
- `else
- return (False);
+ `else
+ return (False);
+ `endif
`endif
`ifdef BOOTROM
else if(addr>=`BootRomBase && addr<=`BootRomEnd)
`endif
`ifdef BOOTROM
else if(addr>=`BootRomBase && addr<=`BootRomEnd)