projects
/
shakti-core.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
SDRAM uses SDR0MemBase now
[shakti-core.git]
/
src
/
lib
/
MemoryMap.bsv
diff --git
a/src/lib/MemoryMap.bsv
b/src/lib/MemoryMap.bsv
index f27a45deb1cd4c6c0b3e3f86688ff3fcf849a44c..9281366440bcc2d40cb3997be85864561fe8bc5a 100644
(file)
--- a/
src/lib/MemoryMap.bsv
+++ b/
src/lib/MemoryMap.bsv
@@
-33,6
+33,8
@@
package MemoryMap;
import defined_types::*;
import fast_memory_map::*;
import slow_memory_map::*;
import defined_types::*;
import fast_memory_map::*;
import slow_memory_map::*;
+ `include "slow_instance_defines.bsv"
+ `include "fast_instance_defines.bsv"
`include "instance_defines.bsv"
`include "core_parameters.bsv"
/*========================= */
`include "instance_defines.bsv"
`include "core_parameters.bsv"
/*========================= */
@@
-60,8
+62,8
@@
endfunction
function Bool is_IO_Addr(Bit#(`PADDR) addr); // TODO Shuold be PADDR
if(addr>=`DebugBase && addr<=`DebugEnd)
return (True);
function Bool is_IO_Addr(Bit#(`PADDR) addr); // TODO Shuold be PADDR
if(addr>=`DebugBase && addr<=`DebugEnd)
return (True);
- `ifdef SDR0
_0_
Base
- else if(addr>=`SDR0
_0_Base && addr<=`SDR0_0_
End)
+ `ifdef SDR0
Mem
Base
+ else if(addr>=`SDR0
MemBase && addr<=`SDR0Mem
End)
`ifdef FlexBus
return (True);
`else
`ifdef FlexBus
return (True);
`else