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Ports: Rename the 'fromXYZPort' to 'fromPort' since it's redundant
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
uart
/
UARTPeriphery.scala
diff --git
a/src/main/scala/devices/uart/UARTPeriphery.scala
b/src/main/scala/devices/uart/UARTPeriphery.scala
index 5564fef60fd934473aabb779331411cb68188917..cb79845e4879f811dceda48ae6f1a3112537c69a 100644
(file)
--- a/
src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/
src/main/scala/devices/uart/UARTPeriphery.scala
@@
-47,7
+47,7
@@
class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
- def from
UART
Port(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
+ def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()