Ports: Rename the 'fromXYZPort' to 'fromPort' since it's redundant

diff --git a/src/main/scala/devices/gpio/GPIOPins.scala b/src/main/scala/devices/gpio/GPIOPins.scala
index 11723c4d1a6a0b8a985694d2795521dc25b0367e..de086bf9f5dbd94d83fbc672c26d1c33ad2ae082 100644 (file)
--- a/src/main/scala/devices/gpio/GPIOPins.scala
+++ b/src/main/scala/devices/gpio/GPIOPins.scala
@@ -16,7 +16,7 @@ class GPIOPins[T <: Pin] (pingen: ()=> T,  c: GPIOParams) extends Bundle {
   override def cloneType: this.type =
     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
 
-  def fromGPIOPort(port: GPIOPortIO){
+  def fromPort(port: GPIOPortIO){
 
     // This will just match up the components of the Bundle that
     // exist in both.

diff --git a/src/main/scala/devices/gpio/JTAG.scala b/src/main/scala/devices/gpio/JTAG.scala
deleted file mode 100644 (file)
index e10f19b..0000000
--- a/src/main/scala/devices/gpio/JTAG.scala
+++ /dev/null
@@ -1,34 +0,0 @@
-// See LICENSE for license details.
-package sifive.blocks.devices.gpio
-
-import Chisel._
-
-// ------------------------------------------------------------
-// SPI, UART, etc are with their
-// respective packages,
-// This file is for those that don't seem to have a good place
-// to put them otherwise.
-// ------------------------------------------------------------
-
-import freechips.rocketchip.config._
-import freechips.rocketchip.jtag.{JTAGIO}
-import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
-
-class JTAGPins[T <: Pin](pingen: () => T, hasTRSTn: Boolean = true) extends Bundle {
-
-  val TCK         = pingen()
-  val TMS         = pingen()
-  val TDI         = pingen()
-  val TDO        = pingen()
-  val TRSTn = if (hasTRSTn) Option(pingen()) else None
-
-  def fromJTAGPort(jtag: JTAGIO): Unit = {
-    jtag.TCK  := TCK.inputPin (pue = Bool(true)).asClock
-    jtag.TMS  := TMS.inputPin (pue = Bool(true))
-    jtag.TDI  := TDI.inputPin(pue = Bool(true))
-    jtag.TRSTn.foreach{t => t := TRSTn.get.inputPin(pue = Bool(true))}
-
-    TDO.outputPin(jtag.TDO.data)
-    TDO.o.oe := jtag.TDO.driven
-  }
-}

diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala
index 8e17765b908a48511db73f27acd0b1d953b5dbad..bae0bc6b435a1c1ad781ff3b39486fd708b80362 100644 (file)
--- a/src/main/scala/devices/i2c/I2CPins.scala
+++ b/src/main/scala/devices/i2c/I2CPins.scala
@@ -15,7 +15,7 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
   override def cloneType: this.type =
     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
 
-  def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
+  def fromPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
     withClockAndReset(clock, reset) {
       scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
       scl.o.oe := i2c.scl.oe

diff --git a/src/main/scala/devices/jtag/JTAGPins.scala b/src/main/scala/devices/jtag/JTAGPins.scala
new file mode 100644 (file)
index 0000000..342f2b9
--- /dev/null
+++ b/src/main/scala/devices/jtag/JTAGPins.scala
@@ -0,0 +1,33 @@
+// See LICENSE for license details.
+package sifive.blocks.devices.jtag
+
+import Chisel._
+
+// ------------------------------------------------------------
+// SPI, UART, etc are with their respective packages,
+// JTAG doesn't really correspond directly to a device, but it does
+// define pins as those devices do.
+// ------------------------------------------------------------
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.jtag.{JTAGIO}
+import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
+
+class JTAGPins[T <: Pin](pingen: () => T, hasTRSTn: Boolean = true) extends Bundle {
+
+  val TCK         = pingen()
+  val TMS         = pingen()
+  val TDI         = pingen()
+  val TDO        = pingen()
+  val TRSTn = if (hasTRSTn) Option(pingen()) else None
+
+  def fromPort(jtag: JTAGIO): Unit = {
+    jtag.TCK  := TCK.inputPin (pue = Bool(true)).asClock
+    jtag.TMS  := TMS.inputPin (pue = Bool(true))
+    jtag.TDI  := TDI.inputPin(pue = Bool(true))
+    jtag.TRSTn.foreach{t => t := TRSTn.get.inputPin(pue = Bool(true))}
+
+    TDO.outputPin(jtag.TDO.data)
+    TDO.o.oe := jtag.TDO.driven
+  }
+}

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index ff5b6bbe1a20aff22e859e3a27c5b65f1ad0a430..3754f71ca3dbf562d05f3169ba370e9a5e1335ba 100644 (file)
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -20,7 +20,7 @@ class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
   override def cloneType: this.type =
     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
 
-  def fromPWMPort(port: PWMPortIO) {
+  def fromPort(port: PWMPortIO) {
     (pwm zip port.port)  foreach {case (pin, port) =>
       pin.outputPin(port)
     }

diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala
index 4307fadbd71a455cd43500eb2ff81dbed429cd68..780e8cc35f5dc6fffa4321ede941769837cc6965 100644 (file)
--- a/src/main/scala/devices/spi/SPIPins.scala
+++ b/src/main/scala/devices/spi/SPIPins.scala
@@ -14,7 +14,7 @@ class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c)
   override def cloneType: this.type =
     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
 
-  def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool,
+  def fromPort(spi: SPIPortIO, clock: Clock, reset: Bool,
     syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
 
     withClockAndReset(clock, reset) {

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index 5564fef60fd934473aabb779331411cb68188917..cb79845e4879f811dceda48ae6f1a3112537c69a 100644 (file)
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -47,7 +47,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
   override def cloneType: this.type =
     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
 
-  def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
+  def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
     withClockAndReset(clock, reset) {
       txd.outputPin(uart.txd)
       val rxd_t = rxd.inputPin()