Merge remote-tracking branch 'origin/master' into typed_pad_ctrl

diff --cc src/main/scala/devices/uart/UARTPeriphery.scala
index d42850f88eca4388a571ac86e47743c69406beef,677394f2581ca436bbf565af0d4f568cff208c23..5564fef60fd934473aabb779331411cb68188917
--- 1/src/main/scala/devices/uart/UARTPeriphery.scala
--- 2/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@@ -2,11 -2,10 +2,11 @@@
  package sifive.blocks.devices.uart
  
  import Chisel._
 +import chisel3.experimental.{withClockAndReset}
  import freechips.rocketchip.config.Field
- import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+ import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
  import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 -import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
 +import sifive.blocks.devices.pinctrl.{Pin}
  import sifive.blocks.util.ShiftRegisterInit
  
  case object PeripheryUARTKey extends Field[Seq[UARTParams]]