big convert g/s/r mid --> muxid

[ieee754fpu.git] / src / nmutil / multipipe.py

diff --git a/src/nmutil/multipipe.py b/src/nmutil/multipipe.py
index e24703f8fcbea1125c00c1a335ca2bb1290c32aa..3fc58e797090a4b2c730a197ea7ae642db1ed661 100644 (file)
--- a/src/nmutil/multipipe.py
+++ b/src/nmutil/multipipe.py
@@ -15,11 +15,12 @@ from nmigen import Signal, Cat, Const, Mux, Module, Array, Elaboratable
 from nmigen.cli import verilog, rtlil
 from nmigen.lib.coding import PriorityEncoder
 from nmigen.hdl.rec import Record, Layout
 from nmigen.cli import verilog, rtlil
 from nmigen.lib.coding import PriorityEncoder
 from nmigen.hdl.rec import Record, Layout

-from stageapi import _spec
+from nmutil.stageapi import _spec

 
 from collections.abc import Sequence
 
 
 from collections.abc import Sequence
 

-from example_buf_pipe import eq, NextControl, PrevControl, ExampleStage
+from .nmoperator import eq
+from .iocontrol import NextControl, PrevControl

 
 
 class MultiInControlBase(Elaboratable):
 
 
 class MultiInControlBase(Elaboratable):


@@ -185,7 +186,9 @@ class CombMultiOutPipeline(MultiOutControlBase):
             self.stage.setup(m, r_data)
 
         # multiplexer id taken from n_mux
             self.stage.setup(m, r_data)
 
         # multiplexer id taken from n_mux

-        mid = self.n_mux.m_id
+        muxid = self.n_mux.m_id
+        print ("self.n_mux", self.n_mux)
+        print ("self.n_mux.m_id", self.n_mux.m_id)

 
         # temporaries
         p_valid_i = Signal(reset_less=True)
 
         # temporaries
         p_valid_i = Signal(reset_less=True)


@@ -197,13 +200,13 @@ class CombMultiOutPipeline(MultiOutControlBase):
         # the only output "active" is then selected by the muxid
         for i in range(len(self.n)):
             m.d.comb += self.n[i].valid_o.eq(0)
         # the only output "active" is then selected by the muxid
         for i in range(len(self.n)):
             m.d.comb += self.n[i].valid_o.eq(0)

-        data_valid = self.n[mid].valid_o
-        m.d.comb += self.p.ready_o.eq(~data_valid | self.n[mid].ready_i)
+        data_valid = self.n[muxid].valid_o
+        m.d.comb += self.p.ready_o.eq(~data_valid | self.n[muxid].ready_i)

         m.d.comb += data_valid.eq(p_valid_i | \
         m.d.comb += data_valid.eq(p_valid_i | \

-                                    (~self.n[mid].ready_i & data_valid))
+                                    (~self.n[muxid].ready_i & data_valid))

         with m.If(pv):
             m.d.comb += eq(r_data, self.p.data_i)
         with m.If(pv):
             m.d.comb += eq(r_data, self.p.data_i)

-        m.d.comb += eq(self.n[mid].data_o, self.process(r_data))
+        m.d.comb += eq(self.n[muxid].data_o, self.process(r_data))

 
         return m
 
 
         return m
 


@@ -301,8 +304,9 @@ class CombMuxOutPipe(CombMultiOutPipeline):
         # HACK: stage is also the n-way multiplexer
         CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
 
         # HACK: stage is also the n-way multiplexer
         CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
 

-        # HACK: n-mux is also the stage... so set the muxid equal to input mid
-        stage.m_id = self.p.data_i.mid
+        # HACK: n-mux is also the stage... so set the muxid equal to input muxid
+        print ("combmuxout", self.p.data_i.muxid)
+        stage.m_id = self.p.data_i.muxid

 
 
 
 
 
 


@@ -352,6 +356,7 @@ class PriorityCombMuxInPipe(CombMultiInPipeline):
 
 if __name__ == '__main__':
 
 
 if __name__ == '__main__':
 

+    from nmutil.test.example_buf_pipe import ExampleStage

     dut = PriorityCombMuxInPipe(ExampleStage)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_combpipe.il", "w") as f:
     dut = PriorityCombMuxInPipe(ExampleStage)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_combpipe.il", "w") as f: