- m.submodules.dest_l = dest_l = SRLatch() # clock-sync'd
- m.submodules.src1_l = src1_l = SRLatch() # clock-sync'd
- m.submodules.src2_l = src2_l = SRLatch() # clock-sync'd
-
- # destination latch: reset on go_wr HI, set on dest and issue
- m.d.comb += dest_l.s.eq(self.issue_i & self.dest_i)
- m.d.comb += dest_l.r.eq(self.go_wr_i)
-
- # src1 latch: reset on go_rd HI, set on src1_i and issue
- m.d.comb += src1_l.s.eq(self.issue_i & self.src1_i)
- m.d.comb += src1_l.r.eq(self.go_rd_i)
-
- # src2 latch: reset on go_rd HI, set on op2_i and issue
- m.d.sync += src2_l.s.eq(self.issue_i & self.src2_i)
- m.d.sync += src2_l.r.eq(self.go_rd_i)
-
- # FU "Forward Progress" (read out horizontally)
- m.d.comb += self.dest_fwd_o.eq(dest_l.q & self.dest_i)
- m.d.comb += self.src1_fwd_o.eq(src1_l.q & self.src1_i)
- m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.src2_i)
-
- # Register File Select (read out vertically)
- m.d.comb += self.dest_rsel_o.eq(dest_l.q & self.go_wr_i)
- m.d.comb += self.src1_rsel_o.eq(src1_l.q & self.go_rd_i)
- m.d.comb += self.src2_rsel_o.eq(src2_l.q & self.go_rd_i)
+ m.submodules.dest_c = dest_c = SRLatch(sync=False, llen=self.n_reg)
+ src_c = []
+ for i in range(self.n_src):
+ src_l = SRLatch(sync=False, llen=self.n_reg)
+ setattr(m.submodules, "src%d_c" % (i+1), src_l)
+ src_c.append(src_l)
+
+ # connect go_rd / go_wr (dest->wr, src->rd)
+ wr_die = Signal(reset_less=True)
+ rd_die = Signal(reset_less=True)
+ m.d.comb += wr_die.eq(self.go_wr_i | self.go_die_i)
+ m.d.comb += rd_die.eq(self.go_rd_i | self.go_die_i)
+ m.d.comb += dest_c.r.eq(Repl(wr_die, self.n_reg))
+ for i in range(self.n_src):
+ m.d.comb += src_c[i].r.eq(Repl(rd_die, self.n_reg))
+
+ # connect input reg bit (unary)
+ i_ext = Repl(self.issue_i, self.n_reg)
+ m.d.comb += dest_c.s.eq(i_ext & self.dest_i)
+ for i in range(self.n_src):
+ m.d.comb += src_c[i].s.eq(i_ext & self.src_i[i])
+
+ # connect up hazard checks: read-after-write and write-after-read
+ m.d.comb += self.dest_fwd_o.eq(dest_c.q & self.rd_pend_i)
+ for i in range(self.n_src):
+ m.d.comb += self.src_fwd_o[i].eq(src_c[i].q & self.wr_pend_i)
+
+ # connect reg-sel outputs
+ rd_ext = Repl(self.go_rd_i, self.n_reg)
+ wr_ext = Repl(self.go_wr_i, self.n_reg)
+ m.d.comb += self.dest_rsel_o.eq(dest_c.qlq & wr_ext)
+ for i in range(self.n_src):
+ m.d.comb += self.src_rsel_o[i].eq(src_c[i].qlq & rd_ext)
+
+ # to be accumulated to indicate if register is in use (globally)
+ # after ORing, is fed back in to rd_pend_i / wr_pend_i
+ src_q = []
+ for i in range(self.n_src):
+ src_q.append(src_c[i].qlq)
+ m.d.comb += self.v_rd_rsel_o.eq(Cat(*src_q).bool())
+ m.d.comb += self.v_wr_rsel_o.eq(dest_c.qlq)