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fix some of instantiation errors in opencores_ethmac.py
[soc.git]
/
src
/
soc
/
bus
/
opencores_ethmac.py
diff --git
a/src/soc/bus/opencores_ethmac.py
b/src/soc/bus/opencores_ethmac.py
index 3078fa67dc0aa07c99f42af24965d45040336204..5720c1ce65ce4cc06b920f30e5c800c1cfa5b3ca 100644
(file)
--- a/
src/soc/bus/opencores_ethmac.py
+++ b/
src/soc/bus/opencores_ethmac.py
@@
-111,6
+111,7
@@
class EthMAC(Elaboratable):
def elaborate(self, platform):
m = Module()
comb = m.d.comb
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ idx = self.idx
# Calculate arbiter bus address
wb_master_bus_adr = Signal(32)
# Calculate arbiter bus address
wb_master_bus_adr = Signal(32)
@@
-119,7
+120,6
@@
class EthMAC(Elaboratable):
# create definition of external verilog EthMAC code here, so that
# nmigen understands I/O directions (defined by i_ and o_ prefixes)
# create definition of external verilog EthMAC code here, so that
# nmigen understands I/O directions (defined by i_ and o_ prefixes)
- idx = self.idx
ethmac = Instance("eth_top",
# Clock/reset (use DomainRenamer if needed)
i_wb_clk_i=ClockSignal(),
ethmac = Instance("eth_top",
# Clock/reset (use DomainRenamer if needed)
i_wb_clk_i=ClockSignal(),