+ if name == 'fast1':
+ return e.read_fast1.ok, e.read_fast1.data
+ if name == 'fast2':
+ return e.read_fast2.ok, e.read_fast2.data
+
+ # SPR regfile
+
+ if regfile == 'SPR':
+ # SPR register numbering is *binary* encoded
+ if name == 'spr1':
+ return e.read_spr1.ok, e.read_spr1.data
+
+ assert False, "regspec not found %s %s" % (regfile, name)
+
+
+def regspec_decode_write(e, regfile, name):
+ """regspec_decode_write
+ """
+
+ # INT regfile
+
+ if regfile == 'INT':
+ # Int register numbering is *unary* encoded
+ if name == 'o': # RT
+ return e.write_reg, e.write_reg.data
+ if name == 'o1': # RA (update mode: LD/ST EA)
+ return e.write_ea, e.write_ea.data
+
+ # CR regfile
+
+ if regfile == 'CR':
+ # CRRegs register numbering is *unary* encoded
+ # *sigh*. numbering inverted on part-CRs. because POWER.
+ if name == 'full_cr': # full CR (from FXM field)
+ return e.do.write_cr_whole.ok, e.do.write_cr_whole.data
+ if name == 'cr_a': # CR A
+ return e.write_cr, 1<<(7-e.write_cr.data)
+
+ # XER regfile
+
+ if regfile == 'XER':
+ # XERRegs register numbering is *unary* encoded
+ SO = 1<<XERRegs.SO
+ CA = 1<<XERRegs.CA
+ OV = 1<<XERRegs.OV
+ if name == 'xer_so':
+ return e.xer_out, SO # hmmm
+ if name == 'xer_ov':
+ return e.xer_out, OV # hmmm
+ if name == 'xer_ca':
+ return e.xer_out, CA # hmmm
+
+ # STATE regfile
+
+ if regfile == 'STATE':
+ # STATE register numbering is *unary* encoded
+ PC = 1<<StateRegs.PC
+ MSR = 1<<StateRegs.MSR