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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
decoder
/
power_regspec_map.py
diff --git
a/src/soc/decoder/power_regspec_map.py
b/src/soc/decoder/power_regspec_map.py
index 6c1e76e7e6097dec8b3607ff6b0b1ca479ba3161..0f5bce328248a18bd6f15b011f7f02d1e4d11ba2 100644
(file)
--- a/
src/soc/decoder/power_regspec_map.py
+++ b/
src/soc/decoder/power_regspec_map.py
@@
-36,7
+36,7
@@
see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
"""
from nmigen import Const
from soc.regfile.regfiles import XERRegs, FastRegs, StateRegs
"""
from nmigen import Const
from soc.regfile.regfiles import XERRegs, FastRegs, StateRegs
-from
soc
.decoder.power_enums import CryIn
+from
openpower
.decoder.power_enums import CryIn
def regspec_decode_read(e, regfile, name):
def regspec_decode_read(e, regfile, name):
@@
-77,10
+77,10
@@
def regspec_decode_read(e, regfile, name):
if name == 'xer_so':
# SO needs to be read for overflow *and* for creation
# of CR0 and also for MFSPR
if name == 'xer_so':
# SO needs to be read for overflow *and* for creation
# of CR0 and also for MFSPR
- return ((e.do.oe.oe[0] & e.do.oe.o
e_o
k) | (e.xer_in & SO == SO)|
+ return ((e.do.oe.oe[0] & e.do.oe.ok) | (e.xer_in & SO == SO)|
(e.do.rc.rc & e.do.rc.ok)), SO
if name == 'xer_ov':
(e.do.rc.rc & e.do.rc.ok)), SO
if name == 'xer_ov':
- return ((e.do.oe.oe[0] & e.do.oe.o
e_o
k) |
+ return ((e.do.oe.oe[0] & e.do.oe.ok) |
(e.xer_in & CA == CA)), OV
if name == 'xer_ca':
return ((e.do.input_carry == CryIn.CA.value) |
(e.xer_in & CA == CA)), OV
if name == 'xer_ca':
return ((e.do.input_carry == CryIn.CA.value) |