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rename PLRU modules to avoid conflict in microwatt
[soc.git]
/
src
/
soc
/
experiment
/
dcache.py
diff --git
a/src/soc/experiment/dcache.py
b/src/soc/experiment/dcache.py
index 917e9818999538375ac3ef0e88b4b911687f69c1..f2e4360abc5c68d87a6e3c923a5a5388fa0e0899 100644
(file)
--- a/
src/soc/experiment/dcache.py
+++ b/
src/soc/experiment/dcache.py
@@
-847,7
+847,7
@@
class DCache(Elaboratable, DCacheConfig):
return
# suite of PLRUs with a selection and output mechanism
return
# suite of PLRUs with a selection and output mechanism
- tlb_plrus = PLRUs(self.TLB_SET_SIZE, self.TLB_WAY_BITS)
+ tlb_plrus = PLRUs(
"d_tlb",
self.TLB_SET_SIZE, self.TLB_WAY_BITS)
m.submodules.tlb_plrus = tlb_plrus
comb += tlb_plrus.way.eq(r1.tlb_hit.way)
comb += tlb_plrus.valid.eq(r1.tlb_hit.valid)
m.submodules.tlb_plrus = tlb_plrus
comb += tlb_plrus.way.eq(r1.tlb_hit.way)
comb += tlb_plrus.valid.eq(r1.tlb_hit.valid)
@@
-953,7
+953,8
@@
class DCache(Elaboratable, DCacheConfig):
return
# suite of PLRUs with a selection and output mechanism
return
# suite of PLRUs with a selection and output mechanism
- m.submodules.plrus = plrus = PLRUs(self.NUM_LINES, self.WAY_BITS)
+ m.submodules.plrus = plrus = PLRUs("dtag", self.NUM_LINES,
+ self.WAY_BITS)
comb += plrus.way.eq(r1.hit_way)
comb += plrus.valid.eq(r1.cache_hit)
comb += plrus.index.eq(r1.hit_index)
comb += plrus.way.eq(r1.hit_way)
comb += plrus.valid.eq(r1.cache_hit)
comb += plrus.index.eq(r1.hit_index)