- # 6 == log2(64) because we have 64-bit values
- grev = GRev(log2_width=(XLEN-1).bit_length())
- m.submodules.grev = grev
- with m.If(op.is_32bit):
- # 32-bit, so input is lower 32-bits zero-extended
- comb += grev.input.eq(self.i.ra[0:32])
- # 32-bit, so we only feed in log2(32) == 5 bits
- comb += grev.chunk_sizes.eq(self.i.rb[0:5])
- with m.Else():
- comb += grev.input.eq(self.i.ra)
- comb += grev.chunk_sizes.eq(self.i.rb)