m.submodules.bitwise_lut = bitwise_lut
comb += bitwise_lut.inputs[0].eq(self.i.rb)
comb += bitwise_lut.inputs[1].eq(self.i.ra)
comb += bitwise_lut.inputs[2].eq(self.i.rc)
# 6 == log2(64) because we have 64-bit values
m.submodules.bitwise_lut = bitwise_lut
comb += bitwise_lut.inputs[0].eq(self.i.rb)
comb += bitwise_lut.inputs[1].eq(self.i.ra)
comb += bitwise_lut.inputs[2].eq(self.i.rc)
# 6 == log2(64) because we have 64-bit values