- with m.If((dut.wr_addr_i == a_const)):
- for i in range(dut.we_width):
- with m.If(we_mask[i] & dut.wr_we_i[i]):
- m.d.sync += d_reg.eq(dut.wr_data_i.word_select(i, gran))
- m.d.sync += wrote.eq(1)
- m.d.sync += wrote_phase.eq(phase)
+ with m.If((dut.wr_addr_i == a_const)
+ & dut.wr_we_i.bit_select(lane, 1)):
+ m.d.sync += d_reg.eq(dut.wr_data_i.word_select(lane, gran))
+ m.d.sync += wrote.eq(1)
+ m.d.sync += wrote_phase.eq(phase)