-Normally if the processor speed were lowered it would have an adverse
-impact on instruction latency.
+As described earlier, normally if the processor speed were lowered it
+would have an adverse impact on instruction latency. With the transparent
+latches bypassed and with plenty of time to stabilise at the lower speed,
+two back-to-back stages now comprise a *single* pipeline stage, and thus,
+even if the processor speed is halved,
+*so is the length of the overall pipeline* and thus the instruction
+completion time remains the same.