re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / .gitignore

diff --git a/.gitignore b/.gitignore
index f0191cf1d2148f0a4a02fa352a294f2862900460..7390ffca2f52bda03aea67c692bf2f8c76767af6 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -13,3 +13,5 @@
 *.snm
 *.vrb
 *.synctex.gz
+
+__pycache__