add SVP64 intro page

[libreriscv.git] / 180nm_Oct2020.mdwn

diff --git a/180nm_Oct2020.mdwn b/180nm_Oct2020.mdwn
index d0976458c9c83726f6626babbc42f7e37156fe36..9f948f55165456a72961f76c4e704de006d7393a 100644 (file)
--- a/180nm_Oct2020.mdwn
+++ b/180nm_Oct2020.mdwn
@@ -1,5 +1,7 @@
 # 180 nm ASIC plan for Oct 2020
 
+NOTE: moved to Jun 9th 2021 (sigh should not have put a date in the page name, oh well)
+
 This page is for discussion of what we can aim for and reasonably achieve.
 To be expanded with links to bugreports
 
@@ -28,6 +30,7 @@ Links:
 * [[180nm_Oct2020/interfaces]] we need as a bare minimum include JTAG,
   GPIO, EINT, SPI and QSPI, I2C, UART16550, LPC (from Raptor Engineering)
   and that actually might even be it.
+* [[180nm_Oct2020/ls180]] actual auto-generated pinouts by pinmux program
 
 ## Secondary priorities
 
@@ -55,12 +58,28 @@ Links:
 * Rudi from <http://asics.ws> to cover the interface set
 * [[lkcl]] for the scoreboard systems
 * [[programmerjake]] TODO
-* [[Yehowshua_Immanuel]] - Delegate interfaces and do timeline/cost projections
-* [[mnolan]] pipelines 
-* [[tplaten]] TODO
+* [[tplaten]] memory and cache
 * [[jock_tanner]] TODO
 * MarketNext TODO
 
-# Preliminary coriolis2 ASIC layout, 02jul2020
+# Preliminary coriolis2 ASIC layout
+
+## 02jul2020 - first version
+
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-July/008438.html>
 
 [[!img 180nm_Oct2020/2020-07-02_19-01.png size="900x" ]]
+
+## 03jul2020 - DIV unit added
+
+[[!img 180nm_Oct2020/2020-07-03_11-04.png size="900x" ]]
+
+## 28dec2020 - End of year progress update
+
+### With blockage layers
+
+[[!img 180nm_Oct2020/2020-12-28.png size="900x" ]]
+
+### Without blockage layers so wires can be seen more clearly
+
+[[!img 180nm_Oct2020/2020-12-28_without_blockages.png size="900x" ]]