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[libreriscv.git] / 3d_gpu.mdwn

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
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--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -4,9 +4,11 @@ Note: this is a **hybrid** CPU, VPU and GPU.  It is not, as many news articles
 are implying, a "dedicated exclusive GPU".  The option exists to **create**
 a stand-alone GPU product (contact us if this is a product that you want).
 Our primary goal is to design a **complete** all-in-one processor
-(System-on-a-Chip) that happens to include a libre-licensed VPU and GPU.
+(System-on-a-Chip) that happens to include libre-licensed VPU and GPU
+accelerated instructions as part of the actual - main - CPU itself.
 
-We seek investors, sponsors, engineers and potential customers, who are
+We seek investors, sponsors (whose contributions thanks to NLNet may be
+tax-deductible), engineers and potential customers, who are
 interested, as a first product, in the creation and use of an entirely
 libre low-power mobile class system-on-a-chip.  Comparative benchmark
 performance, pincount and price is the Allwinner A64, except that the
@@ -27,14 +29,16 @@ the cost of product development when it comes to PCB design and layout:
 We can look at larger higher-power ASICs either later or, if funding
 is made available, immediately.
 
-Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, single core dual issue, around 300 to 350mhz.  This will provide the confidence to go to higher geometries, as well as be a commercially viable embedded product in its own right.
+Recent applications to NLNet (Oct 2019) are for a test chip in 180nm,
+64 bit, single core dual issue, around 300 to 350mhz.  This will provide
+the confidence to go to higher geometries, as well as be a commercially
+viable embedded product in its own right.
 
 # Business Objectives
 
-* the project shall be a hybrid CPU-GPU because if it is not, the
-  complexity involved in developing a split shared-memory CPU-GPU both
-  at a hardware and a software level will be so costly it will jeapordise
-  the project.
+See [[3d_gpu/business_objectives]]
+
+* the project shall be a hybrid CPU-GPU-VPU
 * the project shall be commercial and mass-volume (100 million units
   and above)
 * the project shall be entirely transparent so that end-users will be
@@ -44,6 +48,26 @@ Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, si
   and aiding and assisting developers AND BUSINESSES in debugging and thus
   hugely saving them money.
 
+Reasoning:
+
+* If the processor is not a hybrid CPU-GPU-VPU, the
+  complexity involved in developing a split shared-memory CPU-GPU both
+  at a hardware and a software level will be so costly it will jeapordise
+  the project.
+* The project is commercial and mass-volume because there are plenty
+  of academic designs (none of them reaching production where people
+  may benefit), and "Open" designs, created by the Open Hardware
+  Community, sadly due to the high cost of producing ASICs, tend to be
+  focussed on markets that would have been great about twenty to thirty
+  years ago.
+* Transparency is a key business objective.  It is a Unique Selling Point
+  that the processor is developed in a fashion that, should it be
+  independently audited, no opportunity for spying back-door co-processors
+  will be found to have "made their way surreptitiously - or overtly -
+  into the design".  Yes, GCHQ: I know about the conversation you had
+  with nCipher (and, to their everlasting credit, that they told you
+  to take a hike)
+
 # Links:
 
 * [[shakti/m_class/libre_3d_gpu]]
@@ -51,6 +75,7 @@ Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, si
 * [[resources]]
 * [[overview]]
 * [[3d_gpu/funding]]
+* [[3d_gpu/architecture]]
 * Founding [[charter]]
 * Mailing list <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/>
 * Crowdsupply page <https://www.crowdsupply.com/libre-risc-v/m-class>