bug 1244: add sv.lbz ffirst image

[libreriscv.git] / 3d_gpu.mdwn

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index ef465717b76a69c99cb3917228975d9b2e6260f4..1defb461d1283bb35645f42966f9f18c7a1d3ef2 100644 (file)
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -1,4 +1,4 @@
-See architectural details [here](./architecture) and [[gaddie]] pitch
+See architectural details [here](./architecture), [[gaddie]] pitch and [[business_plan]]
 
 # Hybrid 3D GPU / CPU / VPU
 
@@ -45,6 +45,19 @@ See [[3d_gpu/articles]] online.
 
 # Progress:
 
+* Dec 2021 first MMU unit tests pass, running microwatt mmu.bin.
+  Shows MMU and L1 D/I-Caches as functional in simulation.
+* Apr 2021 cocotb simulation of 180nm ASIC implemented. JTAG TAP
+  confirmed functional on ECP5 and simulation.  FreePDK-c4m45
+  created by <https://chips4makers.io>
+* Mar 2021 first SVP64 OpenPOWER augmented Cray-style instructions executed.
+  NGI POINTER EUR 200,000 grant submitted.
+* Feb 2021 FOSDEM2021, Simple-V SVP64 implementation starts in
+  simulator and Test Issuer
+* Jan 2021 FOSDEM2021 talks confirmed, NLnet crypto-primitives proposal
+  submitted, budget agreed for basic binutils and gcc SVP64 support
+* Dec 2020 work on [[openpower/sv/svp64]] started
+* Nov 2020 dry-run 180nm GDSII sent to IMEC
 * Oct 2020 [[180nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated
   for 180nm test ASIC, GDSII deadline set of Dec 2nd.
 * Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]]