Note: this is a **hybrid** CPU, VPU and GPU. It is not, as many news articles
are implying, a "dedicated exclusive GPU". The option exists to **create**
-a stand-alone GPU product. It is being *designed* to be a **complete**
-all-in-one processor (System-on-a-Chip).
+a stand-alone GPU product (contact us if this is a product that you want).
+Our primary goal is to design a **complete** all-in-one processor
+(System-on-a-Chip) that happens to include a libre-licensed VPU and GPU.
We seek investors, sponsors, engineers and potential customers, who are
interested in the creation and use of an entirely libre low-power mobile
price is the Allwinner A64, except that the power budget target is 2.5 watts
in a 16x16mm 320 to 360 pin 0.8mm FBGA package.
+The lower pincount, lower power, and higher BGA pitch is all to reduce
+the cost of product development when it comes to PCB design and layout:
+
+* Above 4 watts requires metal packages, thermal management and much
+ pricier PMICs.
+* 0.6mm pitch BGA and below requires much more expensive PCBA techniques.
+* Above 600 pins begins to reduce production yields as well as increase
+ the cost of testing and packaging.
+
+We can look at larger higher-power ASICs either later or, if funding
+is made available, immediately.
+
See:
* [[shakti/m_class/libre_3d_gpu]]
* Bugtracker <http://bugs.libre-riscv.org>
* Kazan Vulkan Driver (including 3D engine) <https://salsa.debian.org/Kazan-team/kazan>
* [NLNet 2019 Milestones](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
+* NLNet Project Page <https://nlnet.nl/project/Libre-RISCV/>
Progress:
+* Jul 2019: Sponsorship from Purism received. IEEE754 FP Mul, Add, DIV,
+ FCLASS and FCVT pipelines completed.
+* Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed.
+* May 2019: 6600-style scoreboard started
* Apr 2019: NLnet funding approved by independent review committee
* Mar 2019: NLnet funding application first and second phase passed
* Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD
* <https://www.reddit.com/domain/libre-riscv.org/>
* <https://hardware.slashdot.org/comments.pl?sid=13447940&cid=58160868>
* <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1080755-libre-risc-v-gpu-aiming-for-2-5-watt-power-draw-continues-being-plotted/page5>
+* <https://www.phoronix.com/forums/forum/hardware/processors-memory/1070828-more-details-on-the-proposed-simple-v-extension-to-risc-v-for-gpu-workloads>
+* <https://slashdot.org/submission/9750302/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
+* <https://hardware.slashdot.org/story/19/06/02/0153243/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
+* <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1104124-libre-risc-v-snags-50k-eur-grant-to-work-on-its-risc-v-3d-gpu-chip/page6>
+* <https://heise.de/-4242802>
# Information Resources and Tutorials
* <http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02>
* <https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf>
* <http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf>
+* <https://youtu.be/o5Ihqg72T3c>
+* <http://flopoco.gforge.inria.fr/>
+* Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
# Analog Simulation
projects / libreriscv.git / blobdiff