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[libreriscv.git] / 3d_gpu.mdwn

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
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+++ b/3d_gpu.mdwn
@@ -16,7 +16,8 @@ accelerated instructions as part of the actual - main - CPU itself.  This greatl
 We seek investors, sponsors (whose contributions thanks to NLNet may be
 tax-deductible), engineers and potential customers, who are
 interested, as a first product, in the creation and use of an entirely
-libre low-power mobile class system-on-a-chip.  Comparative benchmark
+libre low-power mobile class system-on-a-chip
+[[shakti/m_class/]].  Comparative benchmark
 performance, pincount and price is the Allwinner A64, except that the
 power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
 FBGA package.  Instead of single-issue higher clock rate, the design is
@@ -44,7 +45,7 @@ See [[3d_gpu/articles]] online.
 
 # Progress:
 
-* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful. 180nm ASIC pinouts started.
+* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]]
 * Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation
 * Jul 2020: first ppc64le "hello world" binary executed.  80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.
 * Jun 2020: core unit tests and pipeline formal correctness proofs in place.