add youtube video first boot on ECP5

[libreriscv.git] / 3d_gpu.mdwn

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 2d60d8a38e0d490929ff4d5977f9748e63e99255..3a87aee52f86bf6bd58a167d2b794818b3938d73 100644 (file)
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -11,7 +11,7 @@ are implying, a "dedicated exclusive GPU".  The option exists to *create*
 a stand-alone GPU product (contact us if this is a product that you want).
 Our primary goal is to design a **complete** all-in-one processor
 (System-on-a-Chip) that happens to include libre-licensed VPU and GPU
-accelerated instructions as part of the actual - main - CPU itself.
+accelerated instructions as part of the actual - main - CPU itself.  This greatly simplifies driver development, applications integration and debugging, reducing costs and time to market in the process.
 
 We seek investors, sponsors (whose contributions thanks to NLNet may be
 tax-deductible), engineers and potential customers, who are
@@ -44,7 +44,9 @@ See [[3d_gpu/articles]] online.
 
 # Progress:
 
-* Jul 2020: first ppc64le "hello world" binary executed.  80,000 gate coriolis2 auto-layout completed with 99.95% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.
+* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful.
+* Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation
+* Jul 2020: first ppc64le "hello world" binary executed.  80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.
 * Jun 2020: core unit tests and pipeline formal correctness proofs in place.
 * May 2020: first integer pipelines (ALU, Logical, Branch, Trap, SPR, ShiftRot, Mul, Div) and register files (XER, CR, INT, FAST, SPR) started.
 * Mar 2020: Coriolis2 Layout experiments successful. 6600 Memory Architecture
@@ -81,3 +83,4 @@ See [[3d_gpu/articles]] online.
 # Drivers
 
 * [[3d_gpu/opencl]]
+* [[3d_gpu/mesa]]