extend gaddie pitch

[libreriscv.git] / 3d_gpu.mdwn

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 3a7d58962897c513447fb70bc614cb98a36eccd9..759e433c4772873e44cb4d6bcf9e14d4daf34791 100644 (file)
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -1,5 +1,32 @@
 See architectural details [here](./architecture)
 
+# "Gaddie Pitch" (1) for LibreSOC
+
+| What we do               | Benefits              | Feelings                |
+| ------------------------ | --------------------- | ----------------------- |
+| design high-performance  | No spying backdoors,  | Much less frustrated    |
+| efficient and simpler    | greatly reduced time  | when developing products|
+| processors with built-in | and cost to market    | using e.g. China-based  |
+| 3D and Video capability  | Simpler debugging     | products.  End-customer |
+| in a fully-transparent   | Full transparency     | stops complaining,      |
+| fashion.                 | for their customers   | Risk and worry gone.    |
+
+## You know how...
+
+You know how for computers, you really have no idea how they work? And
+how you keep having to replace them with upgrades?  Turns out that
+it's very difficult for medium-sized businesses to design lower-cost products
+because the only cheap processors (almost always from China) do not respect
+Copyright law and provide almost zero documentation.
+
+## Well what we do is...
+
+Well, what we do is: design processors that have full transparency
+## In fact...
+
+# "Gaddie Pitch" (2) for LibreSOC
+
+
 # Hybrid 3D GPU / CPU / VPU
 
 Creating a trustworthy processor for the world.
@@ -45,6 +72,8 @@ See [[3d_gpu/articles]] online.
 
 # Progress:
 
+* Oct 2020 [[180nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated
+  for 180nm test ASIC, GDSII deadline set of Dec 2nd.
 * Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]]
 * Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation
 * Jul 2020: first ppc64le "hello world" binary executed.  80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.