add gaddie pitch section for LibreSOC

[libreriscv.git] / 3d_gpu.mdwn

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 113493e34fc2c66b58779640da027e38c99841c6..a385152b1216517e41e785d1b66b962916dfd1a1 100644 (file)
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -1,5 +1,16 @@
 See architectural details [here](./architecture)
 
+# "Gaddie Pitch" for LibreSOC
+
+| What we do               | Benefits              | Feelings                |
+| ------------------------ | --------------------- | ----------------------- |
+| design high-performance  | No spying backdoors,  | Much less frustrated    |
+| efficient and simpler    | greatly reduced time  | when developing products|
+| processors with built-in | and cost to market    | using e.g. China-based  |
+| 3D and Video capability  | Simpler debugging     | products.  End-customer |
+| in a fully-transparent   | Full transparency     | stops complaining,      |
+| fashion.                 | for their customers   | Risk and worry gone.    |
+
 # Hybrid 3D GPU / CPU / VPU
 
 Creating a trustworthy processor for the world.
@@ -45,7 +56,7 @@ See [[3d_gpu/articles]] online.
 
 # Progress:
 
-* Oct 2020 [[80nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated
+* Oct 2020 [[180nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated
   for 180nm test ASIC, GDSII deadline set of Dec 2nd.
 * Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]]
 * Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation