add gaddie pitch section for LibreSOC

[libreriscv.git] / 3d_gpu.mdwn

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index a467339b49fec4fe70420cd9ce3f9f6137ffac86..a385152b1216517e41e785d1b66b962916dfd1a1 100644 (file)
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -1,5 +1,16 @@
 See architectural details [here](./architecture)
 
+# "Gaddie Pitch" for LibreSOC
+
+| What we do               | Benefits              | Feelings                |
+| ------------------------ | --------------------- | ----------------------- |
+| design high-performance  | No spying backdoors,  | Much less frustrated    |
+| efficient and simpler    | greatly reduced time  | when developing products|
+| processors with built-in | and cost to market    | using e.g. China-based  |
+| 3D and Video capability  | Simpler debugging     | products.  End-customer |
+| in a fully-transparent   | Full transparency     | stops complaining,      |
+| fashion.                 | for their customers   | Risk and worry gone.    |
+
 # Hybrid 3D GPU / CPU / VPU
 
 Creating a trustworthy processor for the world.
@@ -11,12 +22,13 @@ are implying, a "dedicated exclusive GPU".  The option exists to *create*
 a stand-alone GPU product (contact us if this is a product that you want).
 Our primary goal is to design a **complete** all-in-one processor
 (System-on-a-Chip) that happens to include libre-licensed VPU and GPU
-accelerated instructions as part of the actual - main - CPU itself.
+accelerated instructions as part of the actual - main - CPU itself.  This greatly simplifies driver development, applications integration and debugging, reducing costs and time to market in the process.
 
 We seek investors, sponsors (whose contributions thanks to NLNet may be
 tax-deductible), engineers and potential customers, who are
 interested, as a first product, in the creation and use of an entirely
-libre low-power mobile class system-on-a-chip.  Comparative benchmark
+libre low-power mobile class system-on-a-chip
+[[shakti/m_class/]].  Comparative benchmark
 performance, pincount and price is the Allwinner A64, except that the
 power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
 FBGA package.  Instead of single-issue higher clock rate, the design is
@@ -44,9 +56,13 @@ See [[3d_gpu/articles]] online.
 
 # Progress:
 
-* Jul 2020: first ppc64le "hello world" binary executed.  80,000 gate coriolis2 auto-layout completed with 99.95% routing.
+* Oct 2020 [[180nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated
+  for 180nm test ASIC, GDSII deadline set of Dec 2nd.
+* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]]
+* Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation
+* Jul 2020: first ppc64le "hello world" binary executed.  80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.
 * Jun 2020: core unit tests and pipeline formal correctness proofs in place.
-* May 2020: first pipelines and register files started.
+* May 2020: first integer pipelines (ALU, Logical, Branch, Trap, SPR, ShiftRot, Mul, Div) and register files (XER, CR, INT, FAST, SPR) started.
 * Mar 2020: Coriolis2 Layout experiments successful. 6600 Memory Architecture
   exploration started.  OpenPOWER ISA decoder started.  Two new people:
   Alain and Jock.
@@ -81,3 +97,4 @@ See [[3d_gpu/articles]] online.
 # Drivers
 
 * [[3d_gpu/opencl]]
+* [[3d_gpu/mesa]]