add sbi spec

[libreriscv.git] / 3d_gpu.mdwn

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index e3a00a0c484a78a3bb37c07c4a3cb668c4842984..ee19acabfc4af2dd13944f2d72a1c6326890c953 100644 (file)
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -13,7 +13,7 @@ in a 16x16mm 320 to 360 pin 0.8mm FBGA package.
 
 See:
 
-* [[libre_3d_gpu]]
+* [[shakti/m_class/libre_3d_gpu]]
 * [[discussion]]
 * Mailing list <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/>
 * Crowdsupply page <https://www.crowdsupply.com/libre-risc-v/m-class>
@@ -24,6 +24,7 @@ See:
 
 Progress:
 
+* Apr 2019: NLnet funding approved by independent review committee
 * Mar 2019: NLnet funding application first and second phase passed
 * Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD
 * Feb 2019: Conversion of John Dawson's IEEE754 FPU to nmigen started
@@ -59,3 +60,23 @@ Progress:
 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html>
 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
+* <http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>
+* <http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu>
+* <https://chips4makers.io/blog/>
+* <https://hackaday.io/project/7817-zynqberry>
+* <https://wiki.f-si.org/index.php/FSiC2019>
+* <https://github.com/efabless/raven-picorv32> - <https://efabless.com>
+* <https://efabless.com/design_catalog/default>
+* <https://toyota-ai.ventures/>
+* <https://github.com/lambdaconcept/minerva>
+* <https://en.wikipedia.org/wiki/Liskov_substitution_principle>
+* <https://en.wikipedia.org/wiki/Principle_of_least_astonishment>
+* <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
+* <https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md>
+
+# Analog Simulation
+
+* <https://github.com/Isotel/mixedsim>
+* <http://www.vlsiacademy.org/open-source-cad-tools.html>
+* <http://ngspice.sourceforge.net/adms.html>
+* <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>