gaddie pitch moving

[libreriscv.git] / 3d_gpu.mdwn

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
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+++ b/3d_gpu.mdwn
@@ -1,3 +1,5 @@
+See architectural details [here](./architecture) and [[gaddie]] pitch
+
 # Hybrid 3D GPU / CPU / VPU
 
 Creating a trustworthy processor for the world.
@@ -9,12 +11,13 @@ are implying, a "dedicated exclusive GPU".  The option exists to *create*
 a stand-alone GPU product (contact us if this is a product that you want).
 Our primary goal is to design a **complete** all-in-one processor
 (System-on-a-Chip) that happens to include libre-licensed VPU and GPU
-accelerated instructions as part of the actual - main - CPU itself.
+accelerated instructions as part of the actual - main - CPU itself.  This greatly simplifies driver development, applications integration and debugging, reducing costs and time to market in the process.
 
 We seek investors, sponsors (whose contributions thanks to NLNet may be
 tax-deductible), engineers and potential customers, who are
 interested, as a first product, in the creation and use of an entirely
-libre low-power mobile class system-on-a-chip.  Comparative benchmark
+libre low-power mobile class system-on-a-chip
+[[shakti/m_class/]].  Comparative benchmark
 performance, pincount and price is the Allwinner A64, except that the
 power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
 FBGA package.  Instead of single-issue higher clock rate, the design is
@@ -42,6 +45,16 @@ See [[3d_gpu/articles]] online.
 
 # Progress:
 
+* Oct 2020 [[180nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated
+  for 180nm test ASIC, GDSII deadline set of Dec 2nd.
+* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]]
+* Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation
+* Jul 2020: first ppc64le "hello world" binary executed.  80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.
+* Jun 2020: core unit tests and pipeline formal correctness proofs in place.
+* May 2020: first integer pipelines (ALU, Logical, Branch, Trap, SPR, ShiftRot, Mul, Div) and register files (XER, CR, INT, FAST, SPR) started.
+* Mar 2020: Coriolis2 Layout experiments successful. 6600 Memory Architecture
+  exploration started.  OpenPOWER ISA decoder started.  Two new people:
+  Alain and Jock.
 * Feb 2020: OpenPower Foundation EULA released. Coriolis2 Layout experimentation begun. Dynamic Partitioned SIMD ALU created.
 * Jan 2020: New team members, Yehowshua and Michael.  Last-minute attendance of FOSDEM2020
 * Dec 2019: Second round NLNet questions answered.  External Review completed.  6 NLNet proposals accepted (EUR 200,000+)
@@ -69,3 +82,8 @@ See [[3d_gpu/articles]] online.
 # Evaluations
 
 * [[openpower]]
+
+# Drivers
+
+* [[3d_gpu/opencl]]
+* [[3d_gpu/mesa]]